#include "hw/irq.h"
#include "hw/southbridge/piix.h"
#include "hw/pci/pci.h"
+#include "hw/ide/piix.h"
#include "hw/isa/isa.h"
#include "hw/intc/i8259.h"
#include "hw/dma/i8257.h"
qemu_irq cpu_intr;
qemu_irq *isa;
- RTCState rtc;
+ MC146818RtcState rtc;
PCIIDEState ide;
UHCIState uhci;
+ PIIX4PMState pm;
/* Reset Control Register */
MemoryRegion rcr_mem;
uint8_t rcr;
}
}
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
-{
- int slot;
-
- slot = PCI_SLOT(pci_dev->devfn);
-
- switch (slot) {
- /* PIIX4 USB */
- case 10:
- return 3;
- /* AMD 79C973 Ethernet */
- case 11:
- return 1;
- /* Crystal 4281 Sound */
- case 12:
- return 2;
- /* PCI slot 1 to 4 */
- case 18 ... 21:
- return ((slot - 18) + irq_num) & 0x03;
- /* Unknown device, don't do any translation */
- default:
- return irq_num;
- }
-}
-
static void piix4_isa_reset(DeviceState *dev)
{
PIIX4State *d = PIIX4_PCI_DEVICE(dev);
pci_conf[0x4c] = 0x4d;
pci_conf[0x4e] = 0x03;
pci_conf[0x4f] = 0x00;
- pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
- pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
- pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
- pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
+ pci_conf[0x60] = 0x80;
+ pci_conf[0x61] = 0x80;
+ pci_conf[0x62] = 0x80;
+ pci_conf[0x63] = 0x80;
pci_conf[0x69] = 0x02;
pci_conf[0x70] = 0x80;
pci_conf[0x76] = 0x0c;
pci_conf[0xab] = 0x00;
pci_conf[0xac] = 0x00;
pci_conf[0xae] = 0x00;
+
+ d->rcr = 0;
}
-static int piix4_ide_post_load(void *opaque, int version_id)
+static int piix4_post_load(void *opaque, int version_id)
{
PIIX4State *s = opaque;
.name = "PIIX4",
.version_id = 3,
.minimum_version_id = 2,
- .post_load = piix4_ide_post_load,
+ .post_load = piix4_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(dev, PIIX4State),
VMSTATE_UINT8_V(rcr, PIIX4State, 3),
s->isa = i8259_init(isa_bus, *i8259_out_irq);
/* initialize ISA irqs */
- isa_bus_irqs(isa_bus, s->isa);
+ isa_bus_register_input_irqs(isa_bus, s->isa);
/* initialize pit */
i8254_pit_init(isa_bus, 0x40, 0, NULL);
if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
return;
}
- pci_ide_create_devs(PCI_DEVICE(&s->ide));
/* USB */
qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2);
return;
}
- pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
+ /* ACPI controller */
+ qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3);
+ if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
+ return;
+ }
+ qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]);
+
+ pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
}
static void piix4_init(Object *obj)
PIIX4State *s = PIIX4_PCI_DEVICE(obj);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
- object_initialize_child(obj, "ide", &s->ide, "piix4-ide");
- object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci");
+ object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
+ object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI);
+
+ object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM);
+ qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100);
+ qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0);
}
static void piix4_class_init(ObjectClass *klass, void *data)
}
type_init(piix4_register_types)
-
-DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
-{
- PCIDevice *pci;
- DeviceState *dev;
- int devfn = PCI_DEVFN(10, 0);
-
- pci = pci_create_simple_multifunction(pci_bus, devfn, true,
- TYPE_PIIX4_PCI_DEVICE);
- dev = DEVICE(pci);
-
- if (isa_bus) {
- *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
- }
-
- if (smbus) {
- pci = pci_new(devfn + 3, TYPE_PIIX4_PM);
- qdev_prop_set_uint32(DEVICE(pci), "smb_io_base", 0x1100);
- qdev_prop_set_bit(DEVICE(pci), "smm-enabled", 0);
- pci_realize_and_unref(pci, pci_bus, &error_fatal);
- qdev_connect_gpio_out(DEVICE(pci), 0,
- qdev_get_gpio_in_named(dev, "isa", 9));
- *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pci), "i2c"));
- }
-
- return dev;
-}