*
* Copyright (c) 2007 CodeSourcery.
*
- * This code is licenced under the GPL
+ * This code is licensed under the GPL
*/
#include "hw.h"
#include "mcf.h"
#include "qemu-timer.h"
+#include "ptimer.h"
#include "sysemu.h"
#include "net.h"
#include "boards.h"
#include "loader.h"
#include "elf.h"
+#include "exec-memory.h"
#define SYS_FREQ 66000000
#define PCSR_PRE_MASK 0x0f00
typedef struct {
+ MemoryRegion iomem;
qemu_irq irq;
ptimer_state *timer;
uint16_t pcsr;
qemu_irq_lower(s->irq);
}
-static void m5208_timer_write(void *opaque, a_target_phys_addr offset,
- uint32_t value)
+static void m5208_timer_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
int prescale;
m5208_timer_update(s);
}
-static uint32_t m5208_timer_read(void *opaque, a_target_phys_addr addr)
+static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
+ unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
switch (addr) {
}
}
-static CPUReadMemoryFunc * const m5208_timer_readfn[] = {
- m5208_timer_read,
- m5208_timer_read,
- m5208_timer_read
+static const MemoryRegionOps m5208_timer_ops = {
+ .read = m5208_timer_read,
+ .write = m5208_timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
- m5208_timer_write,
- m5208_timer_write,
- m5208_timer_write
-};
-
-static uint32_t m5208_sys_read(void *opaque, a_target_phys_addr addr)
+static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
+ unsigned size)
{
switch (addr) {
case 0x110: /* SDCS0 */
}
}
-static void m5208_sys_write(void *opaque, a_target_phys_addr addr,
- uint32_t value)
+static void m5208_sys_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
}
-static CPUReadMemoryFunc * const m5208_sys_readfn[] = {
- m5208_sys_read,
- m5208_sys_read,
- m5208_sys_read
-};
-
-static CPUWriteMemoryFunc * const m5208_sys_writefn[] = {
- m5208_sys_write,
- m5208_sys_write,
- m5208_sys_write
+static const MemoryRegionOps m5208_sys_ops = {
+ .read = m5208_sys_read,
+ .write = m5208_sys_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static void mcf5208_sys_init(qemu_irq *pic)
+static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
{
- int iomemtype;
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);
m5208_timer_state *s;
QEMUBH *bh;
int i;
- iomemtype = cpu_register_io_memory(m5208_sys_readfn,
- m5208_sys_writefn, NULL);
/* SDRAMC. */
- cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
+ memory_region_init_io(iomem, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
+ memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
/* Timers. */
for (i = 0; i < 2; i++) {
- s = (m5208_timer_state *)qemu_mallocz(sizeof(m5208_timer_state));
+ s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
bh = qemu_bh_new(m5208_timer_trigger, s);
s->timer = ptimer_init(bh);
- iomemtype = cpu_register_io_memory(m5208_timer_readfn,
- m5208_timer_writefn, s);
- cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
- iomemtype);
+ memory_region_init_io(&s->iomem, &m5208_timer_ops, s,
+ "m5208-timer", 0x00004000);
+ memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
+ &s->iomem);
s->irq = pic[4 + i];
}
}
-static void mcf5208evb_init(a_ram_addr ram_size,
- const char *boot_device,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename, const char *cpu_model)
+static void mcf5208evb_init(QEMUMachineInitArgs *args)
{
- CPUState *env;
+ ram_addr_t ram_size = args->ram_size;
+ const char *cpu_model = args->cpu_model;
+ const char *kernel_filename = args->kernel_filename;
+ CPUM68KState *env;
int kernel_size;
uint64_t elf_entry;
- a_target_phys_addr entry;
+ hwaddr entry;
qemu_irq *pic;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model)
cpu_model = "m5208";
/* TODO: Configure BARs. */
/* DRAM at 0x40000000 */
- cpu_register_physical_memory(0x40000000, ram_size,
- qemu_ram_alloc(ram_size) | IO_MEM_RAM);
+ memory_region_init_ram(ram, "mcf5208.ram", ram_size);
+ vmstate_register_ram_global(ram);
+ memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Internal SRAM. */
- cpu_register_physical_memory(0x80000000, 16384,
- qemu_ram_alloc(16384) | IO_MEM_RAM);
+ memory_region_init_ram(sram, "mcf5208.sram", 16384);
+ vmstate_register_ram_global(sram);
+ memory_region_add_subregion(address_space_mem, 0x80000000, sram);
/* Internal peripherals. */
- pic = mcf_intc_init(0xfc048000, env);
+ pic = mcf_intc_init(address_space_mem, 0xfc048000, env);
- mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]);
- mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
- mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
+ mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]);
+ mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]);
+ mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]);
- mcf5208_sys_init(pic);
+ mcf5208_sys_init(address_space_mem, pic);
if (nb_nics > 1) {
fprintf(stderr, "Too many NICs\n");
exit(1);
}
- if (nd_table[0].vlan)
- mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36);
+ if (nd_table[0].used)
+ mcf_fec_init(address_space_mem, &nd_table[0],
+ 0xfc030000, pic + 36);
/* 0xfc000000 SCM. */
/* 0xfc004000 XBS. */
exit(1);
}
- kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL,
- 1, ELF_MACHINE, 0);
+ kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
+ NULL, NULL, 1, ELF_MACHINE, 0);
entry = elf_entry;
if (kernel_size < 0) {
kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
projects / mirror_qemu.git / blobdiff