Rename target_phys_addr_t to hwaddr

[mirror_qemu.git] / hw / mcf_uart.c

diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c
index ab0f54f4d43a9a563327d6145b0a727787d93616..d1655f8f2cf90a0ca76a2911efc5cc48df92150b 100644 (file)
--- a/hw/mcf_uart.c
+++ b/hw/mcf_uart.c
@@ -3,11 +3,15 @@
  *
  * Copyright (c) 2007 CodeSourcery.
  *
- * This code is licenced under the GPL
+ * This code is licensed under the GPL
  */
-#include "vl.h"
+#include "hw.h"
+#include "mcf.h"
+#include "qemu-char.h"
+#include "exec-memory.h"
 
 typedef struct {
+    MemoryRegion iomem;
     uint8_t mr[2];
     uint8_t sr;
     uint8_t isr;
@@ -62,7 +66,8 @@ static void mcf_uart_update(mcf_uart_state *s)
     qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
 }
 
-uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
+uint64_t mcf_uart_read(void *opaque, hwaddr addr,
+                       unsigned size)
 {
     mcf_uart_state *s = (mcf_uart_state *)opaque;
     switch (addr & 0x3f) {
@@ -86,6 +91,7 @@ uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
             if (s->fifo_len == 0)
                 s->sr &= ~MCF_UART_RxRDY;
             mcf_uart_update(s);
+            qemu_chr_accept_input(s->chr);
             return val;
         }
     case 0x10:
@@ -107,7 +113,7 @@ static void mcf_uart_do_tx(mcf_uart_state *s)
 {
     if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
         if (s->chr)
-            qemu_chr_write(s->chr, (unsigned char *)&s->tb, 1);
+            qemu_chr_fe_write(s->chr, (unsigned char *)&s->tb, 1);
         s->sr |= MCF_UART_TxEMP;
     }
     if (s->tx_enabled) {
@@ -179,7 +185,8 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
     }
 }
 
-void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
+void mcf_uart_write(void *opaque, hwaddr addr,
+                    uint64_t val, unsigned size)
 {
     mcf_uart_state *s = (mcf_uart_state *)opaque;
     switch (addr & 0x3f) {
@@ -269,7 +276,7 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
 {
     mcf_uart_state *s;
 
-    s = qemu_mallocz(sizeof(mcf_uart_state));
+    s = g_malloc0(sizeof(mcf_uart_state));
     s->chr = chr;
     s->irq = irq;
     if (chr) {
@@ -280,27 +287,20 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
     return s;
 }
 
-
-static CPUReadMemoryFunc *mcf_uart_readfn[] = {
-   mcf_uart_read,
-   mcf_uart_read,
-   mcf_uart_read
-};
-
-static CPUWriteMemoryFunc *mcf_uart_writefn[] = {
-   mcf_uart_write,
-   mcf_uart_write,
-   mcf_uart_write
+static const MemoryRegionOps mcf_uart_ops = {
+    .read = mcf_uart_read,
+    .write = mcf_uart_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
+void mcf_uart_mm_init(MemoryRegion *sysmem,
+                      hwaddr base,
+                      qemu_irq irq,
                       CharDriverState *chr)
 {
     mcf_uart_state *s;
-    int iomemtype;
 
     s = mcf_uart_init(irq, chr);
-    iomemtype = cpu_register_io_memory(0, mcf_uart_readfn,
-                                       mcf_uart_writefn, s);
-    cpu_register_physical_memory(base, 0x40, iomemtype);
+    memory_region_init_io(&s->iomem, &mcf_uart_ops, s, "uart", 0x40);
+    memory_region_add_subregion(sysmem, base, &s->iomem);
 }