#include "qemu/osdep.h"
#include "qemu/units.h"
-#include "qemu-common.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "hw/char/serial.h"
-#include "hw/hw.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/loader.h"
#include "hw/mips/cps.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci-host/xilinx-pcie.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "sysemu/device_tree.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
+#include "sysemu/runstate.h"
#include <libfdt.h>
+#include "qom/object.h"
-#define TYPE_MIPS_BOSTON "mips-boston"
-#define BOSTON(obj) OBJECT_CHECK(BostonState, (obj), TYPE_MIPS_BOSTON)
+#define TYPE_BOSTON "mips-boston"
+typedef struct BostonState BostonState;
+DECLARE_INSTANCE_CHECKER(BostonState, BOSTON,
+ TYPE_BOSTON)
-typedef struct {
+struct BostonState {
SysBusDevice parent_obj;
MachineState *mach;
- MIPSCPSState *cps;
- SerialState *uart;
+ MIPSCPSState cps;
+ SerialMM *uart;
+ Clock *cpuclk;
CharBackend lcd_display;
char lcd_content[8];
hwaddr kernel_entry;
hwaddr fdt_base;
-} BostonState;
+};
enum boston_plat_reg {
PLAT_FPGA_BUILD = 0x00,
PLAT_SYS_CTL = 0x48,
};
-static void boston_lcd_event(void *opaque, int event)
+static void boston_lcd_event(void *opaque, QEMUChrEvent event)
{
BostonState *s = opaque;
if (event == CHR_EVENT_OPENED && !s->lcd_inited) {
case PLAT_DDR3_STATUS:
return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED;
case PLAT_MMCM_DIV:
- gic_freq = mips_gictimer_get_freq(s->cps->gic.gic_timer) / 1000000;
+ gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000;
val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT;
val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT;
val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT;
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void mips_boston_instance_init(Object *obj)
+{
+ BostonState *s = BOSTON(obj);
+
+ s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
+ clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */
+}
+
static const TypeInfo boston_device = {
- .name = TYPE_MIPS_BOSTON,
+ .name = TYPE_BOSTON,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BostonState),
+ .instance_init = mips_boston_instance_init,
};
static void boston_register_types(void)
DeviceState *dev;
MemoryRegion *cfg, *mmio;
- dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST);
+ dev = qdev_new(TYPE_XILINX_PCIE_HOST);
qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
qdev_prop_set_bit(dev, "link_up", link_up);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
{
DeviceState *dev;
BostonState *s;
- Error *err = NULL;
- MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg;
+ MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg;
MemoryRegion *sys_mem = get_system_memory();
XilinxPCIEHost *pcie2;
PCIDevice *ahci;
exit(1);
}
- dev = qdev_create(NULL, TYPE_MIPS_BOSTON);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_BOSTON);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s = BOSTON(dev);
s->mach = machine;
is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
- s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
- qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
-
- object_property_set_str(OBJECT(s->cps), machine->cpu_type, "cpu-type",
- &err);
- object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
- object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
-
- if (err != NULL) {
- error_report("%s", error_get_pretty(err));
- exit(1);
- }
+ object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
+ object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type,
+ &error_fatal);
+ object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus,
+ &error_fatal);
+ qdev_connect_clock_in(DEVICE(&s->cps), "clk-in",
+ qdev_get_clock_out(dev, "cpu-refclk"));
+ sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
- sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
flash = g_new(MemoryRegion, 1);
- memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err);
+ memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB,
+ &error_fatal);
memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
- ddr = g_new(MemoryRegion, 1);
- memory_region_allocate_system_memory(ddr, NULL, "boston.ddr",
- machine->ram_size);
- memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0);
+ memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0);
ddr_low_alias = g_new(MemoryRegion, 1);
memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
- ddr, 0, MIN(machine->ram_size, (256 * MiB)));
+ machine->ram, 0,
+ MIN(machine->ram_size, (256 * MiB)));
memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
xilinx_pcie_init(sys_mem, 0,
0x10000000, 32 * MiB,
0x40000000, 1 * GiB,
- get_cps_irq(s->cps, 2), false);
+ get_cps_irq(&s->cps, 2), false);
xilinx_pcie_init(sys_mem, 1,
0x12000000, 32 * MiB,
0x20000000, 512 * MiB,
- get_cps_irq(s->cps, 1), false);
+ get_cps_irq(&s->cps, 1), false);
pcie2 = xilinx_pcie_init(sys_mem, 2,
0x14000000, 32 * MiB,
0x16000000, 1 * MiB,
- get_cps_irq(s->cps, 0), true);
+ get_cps_irq(&s->cps, 0), true);
platreg = g_new(MemoryRegion, 1);
memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
- get_cps_irq(s->cps, 3), 10000000,
+ get_cps_irq(&s->cps, 3), 10000000,
serial_hd(0), DEVICE_NATIVE_ENDIAN);
lcd = g_new(MemoryRegion, 1);
memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0);
- chr = qemu_chr_new("lcd", "vc:320x240");
+ chr = qemu_chr_new("lcd", "vc:320x240", NULL);
qemu_chr_fe_init(&s->lcd_display, chr, NULL);
qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL,
boston_lcd_event, NULL, s, NULL, true);
fw_size = load_image_targphys(machine->firmware,
0x1fc00000, 4 * MiB);
if (fw_size == -1) {
- error_printf("unable to load firmware image '%s'\n",
+ error_report("unable to load firmware image '%s'",
machine->firmware);
exit(1);
}
} else if (machine->kernel_filename) {
fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s);
if (fit_err) {
- error_printf("unable to load FIT image\n");
+ error_report("unable to load FIT image");
exit(1);
}
gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,
s->kernel_entry, s->fdt_base, is_64b);
} else if (!qtest_enabled()) {
- error_printf("Please provide either a -kernel or -bios argument\n");
+ error_report("Please provide either a -kernel or -bios argument");
exit(1);
}
}
mc->init = boston_mach_init;
mc->block_default_type = IF_IDE;
mc->default_ram_size = 1 * GiB;
+ mc->default_ram_id = "boston.ddr";
mc->max_cpus = 16;
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
}