#include "qemu/osdep.h"
#include "qemu/units.h"
+#include "qemu/bitops.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
-#include "cpu.h"
#include "hw/clock.h"
#include "hw/southbridge/piix.h"
#include "hw/isa/superio.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
-#include "sysemu/sysemu.h"
-#include "sysemu/arch_init.h"
#include "qemu/log.h"
#include "hw/mips/bios.h"
#include "hw/ide.h"
#include "hw/irq.h"
#include "hw/loader.h"
#include "elf.h"
-#include "exec/address-spaces.h"
#include "qom/object.h"
#include "hw/sysbus.h" /* SysBusDevice */
#include "qemu/host-utils.h"
#include "qemu/error-report.h"
#include "hw/misc/empty_slot.h"
#include "sysemu/kvm.h"
-#include "hw/semihosting/semihost.h"
+#include "semihosting/semihost.h"
#include "hw/mips/cps.h"
#include "hw/qdev-clock.h"
-#define ENVP_ADDR 0x80002000l
+#define ENVP_PADDR 0x2000
+#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
#define ENVP_NB_ENTRIES 16
#define ENVP_ENTRY_SIZE 256
Clock *cpuclk;
MIPSCPSState cps;
- qemu_irq i8259[ISA_NUM_IRQS];
};
static struct _loaderparams {
}
}
-static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
- int64_t kernel_entry)
+static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
+ uint64_t kernel_entry)
{
uint16_t *p;
/* li a0,2 */
}
- stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64));
+ stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64));
- stw_p(p++, NM_HI2(ENVP_ADDR - 64));
- /* lui sp,%hi(ENVP_ADDR - 64) */
+ stw_p(p++, NM_HI2(ENVP_VADDR - 64));
+ /* lui sp,%hi(ENVP_VADDR - 64) */
- stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64));
- /* ori sp,sp,%lo(ENVP_ADDR - 64) */
+ stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64));
+ /* ori sp,sp,%lo(ENVP_VADDR - 64) */
- stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR));
+ stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR));
- stw_p(p++, NM_HI2(ENVP_ADDR));
- /* lui a1,%hi(ENVP_ADDR) */
+ stw_p(p++, NM_HI2(ENVP_VADDR));
+ /* lui a1,%hi(ENVP_VADDR) */
- stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR));
- /* ori a1,a1,%lo(ENVP_ADDR) */
+ stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR));
+ /* ori a1,a1,%lo(ENVP_VADDR) */
- stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8));
+ stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8));
- stw_p(p++, NM_HI2(ENVP_ADDR + 8));
- /* lui a2,%hi(ENVP_ADDR + 8) */
+ stw_p(p++, NM_HI2(ENVP_VADDR + 8));
+ /* lui a2,%hi(ENVP_VADDR + 8) */
- stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8));
- /* ori a2,a2,%lo(ENVP_ADDR + 8) */
+ stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8));
+ /* ori a2,a2,%lo(ENVP_VADDR + 8) */
stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
* a2 - 32-bit address of the environment variables table
* a3 - RAM size in bytes
*/
-static void write_bootloader(uint8_t *base, int64_t run_addr,
- int64_t kernel_entry)
+static void write_bootloader(uint8_t *base, uint64_t run_addr,
+ uint64_t kernel_entry)
{
uint32_t *p;
stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
}
- /* lui sp, high(ENVP_ADDR) */
- stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
- /* ori sp, sp, low(ENVP_ADDR) */
- stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
- /* lui a1, high(ENVP_ADDR) */
- stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
- /* ori a1, a1, low(ENVP_ADDR) */
- stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
- /* lui a2, high(ENVP_ADDR + 8) */
- stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
- /* ori a2, a2, low(ENVP_ADDR + 8) */
- stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
+ /* lui sp, high(ENVP_VADDR) */
+ stl_p(p++, 0x3c1d0000 | (((ENVP_VADDR - 64) >> 16) & 0xffff));
+ /* ori sp, sp, low(ENVP_VADDR) */
+ stl_p(p++, 0x37bd0000 | ((ENVP_VADDR - 64) & 0xffff));
+ /* lui a1, high(ENVP_VADDR) */
+ stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff));
+ /* ori a1, a1, low(ENVP_VADDR) */
+ stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff));
+ /* lui a2, high(ENVP_VADDR + 8) */
+ stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff));
+ /* ori a2, a2, low(ENVP_VADDR + 8) */
+ stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff));
/* lui a3, high(ram_low_size) */
stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
/* ori a3, a3, low(ram_low_size) */
}
-static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
+static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
const char *string, ...)
{
va_list ap;
- int32_t table_addr;
+ uint32_t table_addr;
if (index >= ENVP_NB_ENTRIES) {
return;
return;
}
- table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
- prom_buf[index] = tswap32(ENVP_ADDR + table_addr);
+ table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
+ prom_buf[index] = tswap32(ENVP_VADDR + table_addr);
va_start(ap, string);
vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
}
/* Kernel */
-static int64_t load_kernel(void)
+static uint64_t load_kernel(void)
{
- int64_t kernel_entry, kernel_high, initrd_size;
+ uint64_t kernel_entry, kernel_high, initrd_size;
long kernel_size;
ram_addr_t initrd_offset;
int big_endian;
kernel_size = load_elf(loaderparams.kernel_filename, NULL,
cpu_mips_kseg0_to_phys, NULL,
- (uint64_t *)&kernel_entry, NULL,
- (uint64_t *)&kernel_high, NULL, big_endian, EM_MIPS,
+ &kernel_entry, NULL,
+ &kernel_high, NULL, big_endian, EM_MIPS,
1, 0);
if (kernel_size < 0) {
error_report("could not load kernel '%s': %s",
prom_set(prom_buf, prom_index++, "38400n8r");
prom_set(prom_buf, prom_index++, NULL);
- rom_add_blob_fixed("prom", prom_buf, prom_size,
- cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
+ rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);
g_free(prom_buf);
return kernel_entry;
CPUMIPSState *env = &cpu->env;
CPUState *cs = CPU(cpu);
- env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
- ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC);
+ if (ase_mt_available(env)) {
+ env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
+ CP0MVPC0_PTC, 8,
+ smp_cpus * cs->nr_threads - 1);
+ env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
+ CP0MVPC0_PVPE, 4, smp_cpus - 1);
+ }
}
static void main_cpu_reset(void *opaque)
static void mips_create_cpu(MachineState *ms, MaltaState *s,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
- if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) {
+ if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
create_cps(ms, s, cbus_irq, i8259_irq);
} else {
create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
const size_t smbus_eeprom_size = 8 * 256;
uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
- int64_t kernel_entry, bootloader_run_addr;
+ uint64_t kernel_entry, bootloader_run_addr;
PCIBus *pci_bus;
ISABus *isa_bus;
qemu_irq cbus_irq, i8259_irq;
/* For KVM we reserve 1MB of RAM for running bootloader */
if (kvm_enabled()) {
ram_low_size -= 0x100000;
- bootloader_run_addr = 0x40000000 + ram_low_size;
+ bootloader_run_addr = cpu_mips_kvm_um_phys_to_kseg0(NULL, ram_low_size);
} else {
- bootloader_run_addr = 0xbfc00000;
+ bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
}
/* Write a small bootloader to the flash location. */
loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel();
- if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
+ if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
write_bootloader(memory_region_get_ram_ptr(bios),
bootloader_run_addr, kernel_entry);
} else {
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
/* Northbridge */
- pci_bus = gt64120_register(s->i8259);
+ dev = sysbus_create_simple("gt64120", -1, NULL);
+ pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
/*
* The whole address space decoded by the GT-64120A doesn't generate
* exception when accessing invalid memory. Create an empty slot to
/* Interrupt controller */
qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
- for (int i = 0; i < ISA_NUM_IRQS; i++) {
- s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
- }
/* generate SPD EEPROM data */
generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
projects / mirror_qemu.git / blobdiff