*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/i386/pc.h"
+#include "hw/isa/superio.h"
+#include "hw/dma/i8257.h"
#include "hw/char/serial.h"
-#include "hw/block/fdc.h"
#include "net/net.h"
#include "hw/boards.h"
#include "hw/i2c/smbus.h"
-#include "sysemu/block-backend.h"
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "elf.h"
#include "hw/timer/mc146818rtc.h"
#include "hw/timer/i8254.h"
-#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"
#include "hw/sysbus.h" /* SysBusDevice */
#include "qemu/host-utils.h"
#include "sysemu/qtest.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/empty_slot.h"
#include "sysemu/kvm.h"
int i;
/* work in terms of MB */
- ram_size >>= 20;
+ ram_size /= MiB;
while ((ram_size >= 4) && (nbanks <= 2)) {
int sz_log2 = MIN(31 - clz32(ram_size), 14);
}
if (ram_size) {
- fprintf(stderr, "Warning: SPD cannot represent final %dMB"
- " of SDRAM\n", (int)ram_size);
+ warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
+ " of SDRAM", ram_size);
}
/* fill in SPD memory information */
chr = qemu_chr_new("fpga", "vc:320x200");
qemu_chr_fe_init(&s->display, chr, NULL);
qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
- malta_fgpa_display_event, s, NULL, true);
+ malta_fgpa_display_event, NULL, s, NULL, true);
s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
230400, uart_chr, DEVICE_NATIVE_ENDIAN);
static int64_t load_kernel (void)
{
int64_t kernel_entry, kernel_high;
- long initrd_size;
+ long kernel_size, initrd_size;
ram_addr_t initrd_offset;
int big_endian;
uint32_t *prom_buf;
big_endian = 0;
#endif
- if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL,
- (uint64_t *)&kernel_entry, NULL, (uint64_t *)&kernel_high,
- big_endian, EM_MIPS, 1, 0) < 0) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n",
- loaderparams.kernel_filename);
+ kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
+ NULL, (uint64_t *)&kernel_entry, NULL,
+ (uint64_t *)&kernel_high, big_endian, EM_MIPS, 1, 0);
+ if (kernel_size < 0) {
+ error_report("could not load kernel '%s': %s",
+ loaderparams.kernel_filename,
+ load_elf_strerror(kernel_size));
exit(1);
}
- /* Sanity check where the kernel has been linked */
- if (kvm_enabled()) {
- if (kernel_entry & 0x80000000ll) {
+ /* Check where the kernel has been linked */
+ if (kernel_entry & 0x80000000ll) {
+ if (kvm_enabled()) {
error_report("KVM guest kernels must be linked in useg. "
"Did you forget to enable CONFIG_KVM_GUEST?");
exit(1);
}
- xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
+ xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
} else {
- if (!(kernel_entry & 0x80000000ll)) {
- error_report("KVM guest kernels aren't supported with TCG. "
- "Did you unintentionally enable CONFIG_KVM_GUEST?");
- exit(1);
- }
+ /* if kernel entry is in useg it is probably a KVM T&E kernel */
+ mips_um_ksegs_enable();
- xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
+ xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
}
/* load initrd */
if (loaderparams.initrd_filename) {
initrd_size = get_image_size (loaderparams.initrd_filename);
if (initrd_size > 0) {
+ /* The kernel allocates the bootmap memory in the low memory after
+ the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
+ pages. */
initrd_offset = (loaderparams.ram_low_size - initrd_size
+ - (128 * KiB)
- ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
if (kernel_high >= initrd_offset) {
- fprintf(stderr,
- "qemu: memory too small for initial ram disk '%s'\n",
- loaderparams.initrd_filename);
+ error_report("memory too small for initial ram disk '%s'",
+ loaderparams.initrd_filename);
exit(1);
}
initrd_size = load_image_targphys(loaderparams.initrd_filename,
ram_size - initrd_offset);
}
if (initrd_size == (target_ulong) -1) {
- fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
- loaderparams.initrd_filename);
+ error_report("could not load initial ram disk '%s'",
+ loaderparams.initrd_filename);
exit(1);
}
}
}
}
-static void create_cpu_without_cps(const char *cpu_model,
+static void create_cpu_without_cps(const char *cpu_type,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
CPUMIPSState *env;
int i;
for (i = 0; i < smp_cpus; i++) {
- cpu = cpu_mips_init(cpu_model);
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(1);
- }
+ cpu = MIPS_CPU(cpu_create(cpu_type));
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
*cbus_irq = env->irq[4];
}
-static void create_cps(MaltaState *s, const char *cpu_model,
+static void create_cps(MaltaState *s, const char *cpu_type,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
Error *err = NULL;
- s->cps = g_new0(MIPSCPSState, 1);
- object_initialize(s->cps, sizeof(MIPSCPSState), TYPE_MIPS_CPS);
+ s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
- object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
+ object_property_set_str(OBJECT(s->cps), cpu_type, "cpu-type", &err);
object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
if (err != NULL) {
*cbus_irq = NULL;
}
-static void create_cpu(MaltaState *s, const char *cpu_model,
- qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+static void mips_create_cpu(MaltaState *s, const char *cpu_type,
+ qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
- if (cpu_model == NULL) {
-#ifdef TARGET_MIPS64
- cpu_model = "20Kc";
-#else
- cpu_model = "24Kf";
-#endif
- }
-
- if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_model)) {
- create_cps(s, cpu_model, cbus_irq, i8259_irq);
+ if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_type)) {
+ create_cps(s, cpu_type, cbus_irq, i8259_irq);
} else {
- create_cpu_without_cps(cpu_model, cbus_irq, i8259_irq);
+ create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq);
}
}
qemu_irq cbus_irq, i8259_irq;
int piix4_devfn;
I2CBus *smbus;
- int i;
DriveInfo *dinfo;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
- DriveInfo *fd[MAX_FD];
int fl_idx = 0;
int fl_sectors = bios_size >> 16;
int be;
qdev_init_nofail(dev);
- /* Make sure the first 3 serial ports are associated with a device. */
- for(i = 0; i < 3; i++) {
- if (!serial_hds[i]) {
- char label[32];
- snprintf(label, sizeof(label), "serial%d", i);
- serial_hds[i] = qemu_chr_new(label, "null");
- }
- }
-
/* create CPU */
- create_cpu(s, machine->cpu_model, &cbus_irq, &i8259_irq);
+ mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq);
/* allocate RAM */
- if (ram_size > (2048u << 20)) {
- fprintf(stderr,
- "qemu: Too much memory for this machine: %d MB, maximum 2048 MB\n",
- ((unsigned int)ram_size / (1 << 20)));
+ if (ram_size > 2 * GiB) {
+ error_report("Too much memory for this machine: %" PRId64 "MB,"
+ " maximum 2048MB", ram_size / MiB);
exit(1);
}
/* alias for pre IO hole access */
memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
- ram_high, 0, MIN(ram_size, (256 << 20)));
+ ram_high, 0, MIN(ram_size, 256 * MiB));
memory_region_add_subregion(system_memory, 0, ram_low_preio);
/* alias for post IO hole access, if there is enough RAM */
- if (ram_size > (512 << 20)) {
+ if (ram_size > 512 * MiB) {
ram_low_postio = g_new(MemoryRegion, 1);
memory_region_init_alias(ram_low_postio, NULL,
"mips_malta_low_postio.ram",
- ram_high, 512 << 20,
- ram_size - (512 << 20));
- memory_region_add_subregion(system_memory, 512 << 20, ram_low_postio);
+ ram_high, 512 * MiB,
+ ram_size - 512 * MiB);
+ memory_region_add_subregion(system_memory, 512 * MiB,
+ ram_low_postio);
}
- /* generate SPD EEPROM data */
- generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
- generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
-
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
+
/* FPGA */
+
/* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
- malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hds[2]);
+ malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2));
/* Load firmware in flash / BIOS. */
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
bios = pflash_cfi01_get_memory(fl);
fl_idx++;
if (kernel_filename) {
- ram_low_size = MIN(ram_size, 256 << 20);
+ ram_low_size = MIN(ram_size, 256 * MiB);
/* For KVM we reserve 1MB of RAM for running bootloader */
if (kvm_enabled()) {
ram_low_size -= 0x100000;
a neat trick which allows bi-endian firmware. */
#ifndef TARGET_WORDS_BIGENDIAN
{
- uint32_t *end, *addr = rom_ptr(FLASH_ADDRESS);
+ uint32_t *end, *addr;
+ const size_t swapsize = MIN(bios_size, 0x3e0000);
+ addr = rom_ptr(FLASH_ADDRESS, swapsize);
if (!addr) {
addr = memory_region_get_ram_ptr(bios);
}
- end = (void *)addr + MIN(bios_size, 0x3e0000);
+ end = (void *)addr + swapsize;
while (addr < end) {
bswap32s(addr);
addr++;
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
+ pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
+ i8257_dma_init(isa_bus, 0);
+ mc146818_rtc_init(isa_bus, 2000, NULL);
+
+ /* generate SPD EEPROM data */
+ generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
+ generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
g_free(smbus_eeprom_buf);
- pit = pit_init(isa_bus, 0x40, 0, NULL);
- DMA_init(isa_bus, 0);
- /* Super I/O */
- isa_create_simple(isa_bus, "i8042");
-
- rtc_init(isa_bus, 2000, NULL);
- serial_hds_isa_init(isa_bus, 0, 2);
- parallel_hds_isa_init(isa_bus, 1);
-
- for(i = 0; i < MAX_FD; i++) {
- fd[i] = drive_get(IF_FLOPPY, 0, i);
- }
- fdctrl_init_isa(isa_bus, fd);
+ /* Super I/O: SMS FDC37M817 */
+ isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO);
/* Network card */
network_init(pci_bus);
mc->block_default_type = IF_IDE;
mc->max_cpus = 16;
mc->is_default = 1;
+#ifdef TARGET_MIPS64
+ mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
+#else
+ mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
+#endif
}
DEFINE_MACHINE("malta", mips_malta_machine_init)
projects / mirror_qemu.git / blobdiff