#include "hw/empty_slot.h"
#include "sysemu/kvm.h"
#include "exec/semihost.h"
+#include "hw/mips/cps.h"
//#define DEBUG_BOARD_INIT
CharDriverState *display;
char display_text[9];
SerialState *uart;
+ bool display_inited;
} MaltaFPGAState;
#define TYPE_MIPS_MALTA "mips-malta"
typedef struct {
SysBusDevice parent_obj;
+ MIPSCPSState *cps;
qemu_irq *i8259;
} MaltaState;
snprintf(s->display_text, 9, " ");
}
-static void malta_fpga_led_init(CharDriverState *chr)
+static void malta_fgpa_display_event(void *opaque, int event)
{
- qemu_chr_fe_printf(chr, "\e[HMalta LEDBAR\r\n");
- qemu_chr_fe_printf(chr, "+--------+\r\n");
- qemu_chr_fe_printf(chr, "+ +\r\n");
- qemu_chr_fe_printf(chr, "+--------+\r\n");
- qemu_chr_fe_printf(chr, "\n");
- qemu_chr_fe_printf(chr, "Malta ASCII\r\n");
- qemu_chr_fe_printf(chr, "+--------+\r\n");
- qemu_chr_fe_printf(chr, "+ +\r\n");
- qemu_chr_fe_printf(chr, "+--------+\r\n");
+ MaltaFPGAState *s = opaque;
+
+ if (event == CHR_EVENT_OPENED && !s->display_inited) {
+ qemu_chr_fe_printf(s->display, "\e[HMalta LEDBAR\r\n");
+ qemu_chr_fe_printf(s->display, "+--------+\r\n");
+ qemu_chr_fe_printf(s->display, "+ +\r\n");
+ qemu_chr_fe_printf(s->display, "+--------+\r\n");
+ qemu_chr_fe_printf(s->display, "\n");
+ qemu_chr_fe_printf(s->display, "Malta ASCII\r\n");
+ qemu_chr_fe_printf(s->display, "+--------+\r\n");
+ qemu_chr_fe_printf(s->display, "+ +\r\n");
+ qemu_chr_fe_printf(s->display, "+--------+\r\n");
+ s->display_inited = true;
+ }
}
static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
memory_region_add_subregion(address_space, base, &s->iomem_lo);
memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
- s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init);
+ s->display = qemu_chr_new("fpga", "vc:320x200");
+ qemu_chr_add_handlers(s->display, NULL, NULL,
+ malta_fgpa_display_event, s);
s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
230400, uart_chr, DEVICE_NATIVE_ENDIAN);
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x0ff0021c); /* jal 870 */
stl_p(p++, 0x00000000); /* nop */
- stl_p(p++, 0x08000205); /* j 814 */
+ stl_p(p++, 0x1000fff9); /* b 814 */
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x01a00009); /* jalr t5 */
stl_p(p++, 0x01602021); /* move a0,t3 */
}
}
-static void create_cpu(const char *cpu_model,
- qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+static void create_cpu_without_cps(const char *cpu_model,
+ qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
CPUMIPSState *env;
MIPSCPU *cpu;
int i;
- if (cpu_model == NULL) {
-#ifdef TARGET_MIPS64
- cpu_model = "20Kc";
-#else
- cpu_model = "24Kf";
-#endif
- }
for (i = 0; i < smp_cpus; i++) {
cpu = cpu_mips_init(cpu_model);
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- env = &cpu->env;
/* Init internal devices */
- cpu_mips_irq_init_cpu(env);
- cpu_mips_clock_init(env);
+ cpu_mips_irq_init_cpu(cpu);
+ cpu_mips_clock_init(cpu);
qemu_register_reset(main_cpu_reset, cpu);
}
*cbus_irq = env->irq[4];
}
+static void create_cps(MaltaState *s, const char *cpu_model,
+ qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+{
+ Error *err = NULL;
+ s->cps = g_new0(MIPSCPSState, 1);
+
+ object_initialize(s->cps, sizeof(MIPSCPSState), TYPE_MIPS_CPS);
+ qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
+
+ object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
+ object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
+ object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
+ if (err != NULL) {
+ error_report("%s", error_get_pretty(err));
+ exit(1);
+ }
+
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
+
+ *i8259_irq = get_cps_irq(s->cps, 3);
+ *cbus_irq = NULL;
+}
+
+static void create_cpu(MaltaState *s, const char *cpu_model,
+ qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+{
+ if (cpu_model == NULL) {
+#ifdef TARGET_MIPS64
+ cpu_model = "20Kc";
+#else
+ cpu_model = "24Kf";
+#endif
+ }
+
+ if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_model)) {
+ create_cps(s, cpu_model, cbus_irq, i8259_irq);
+ } else {
+ create_cpu_without_cps(cpu_model, cbus_irq, i8259_irq);
+ }
+}
+
static
void mips_malta_init(MachineState *machine)
{
if (!serial_hds[i]) {
char label[32];
snprintf(label, sizeof(label), "serial%d", i);
- serial_hds[i] = qemu_chr_new(label, "null", NULL);
+ serial_hds[i] = qemu_chr_new(label, "null");
}
}
- /* create CPUs */
- create_cpu(machine->cpu_model, &cbus_irq, &i8259_irq);
+ /* create CPU */
+ create_cpu(s, machine->cpu_model, &cbus_irq, &i8259_irq);
/* allocate RAM */
if (ram_size > (2048u << 20)) {
isa_create_simple(isa_bus, "i8042");
rtc_init(isa_bus, 2000, NULL);
- serial_hds_isa_init(isa_bus, 2);
+ serial_hds_isa_init(isa_bus, 0, 2);
parallel_hds_isa_init(isa_bus, 1);
for(i = 0; i < MAX_FD; i++) {