} while (0)
REG32(NWCTRL, 0x0) /* Network Control reg */
+ FIELD(NWCTRL, LOOPBACK , 0, 1)
+ FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1)
+ FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1)
+ FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1)
+ FIELD(NWCTRL, MAN_PORT_EN , 4, 1)
+ FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1)
+ FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1)
+ FIELD(NWCTRL, STATS_WRITE_EN, 7, 1)
+ FIELD(NWCTRL, BACK_PRESSURE, 8, 1)
+ FIELD(NWCTRL, TRANSMIT_START , 9, 1)
+ FIELD(NWCTRL, TRANSMIT_HALT, 10, 1)
+ FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1)
+ FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1)
+ FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1)
+ FIELD(NWCTRL, STATS_READ_SNAP, 14, 1)
+ FIELD(NWCTRL, STORE_RX_TS, 15, 1)
+ FIELD(NWCTRL, PFC_ENABLE, 16, 1)
+ FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1)
+ FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1)
+ FIELD(NWCTRL, TX_LPI_EN, 19, 1)
+ FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1)
+ FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1)
+ FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1)
+ FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1)
+ FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1)
+ FIELD(NWCTRL, PFC_CTRL , 25, 1)
+ FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1)
+ FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1)
+ FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1)
+ FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1)
+ FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1)
+
REG32(NWCFG, 0x4) /* Network Config reg */
+ FIELD(NWCFG, SPEED, 0, 1)
+ FIELD(NWCFG, FULL_DUPLEX, 1, 1)
+ FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1)
+ FIELD(NWCFG, JUMBO_FRAMES, 3, 1)
+ FIELD(NWCFG, PROMISC, 4, 1)
+ FIELD(NWCFG, NO_BROADCAST, 5, 1)
+ FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1)
+ FIELD(NWCFG, UNICAST_HASH_EN, 7, 1)
+ FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1)
+ FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1)
+ FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1)
+ FIELD(NWCFG, PCS_SELECT, 11, 1)
+ FIELD(NWCFG, RETRY_TEST, 12, 1)
+ FIELD(NWCFG, PAUSE_ENABLE, 13, 1)
+ FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2)
+ FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1)
+ FIELD(NWCFG, FCS_REMOVE, 17, 1)
+ FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3)
+ FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2)
+ FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1)
+ FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1)
+ FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1)
+ FIELD(NWCFG, IGNORE_RX_FCS, 26, 1)
+ FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1)
+ FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1)
+ FIELD(NWCFG, NSP_ACCEPT, 29, 1)
+ FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1)
+ FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1)
+
REG32(NWSTATUS, 0x8) /* Network Status reg */
REG32(USERIO, 0xc) /* User IO reg */
+
REG32(DMACFG, 0x10) /* DMA Control reg */
+ FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1)
+ FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1)
+ FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1)
+ FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1)
+ FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1)
+ FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1)
+ FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1)
+ FIELD(DMACFG, RX_BUF_SIZE, 16, 8)
+ FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1)
+ FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1)
+ FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1)
+ FIELD(DMACFG, TX_PBUF_SIZE, 10, 1)
+ FIELD(DMACFG, RX_PBUF_SIZE, 8, 2)
+ FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1)
+ FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1)
+ FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1)
+ FIELD(DMACFG, AMBA_BURST_LEN , 0, 5)
+#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
+
REG32(TXSTATUS, 0x14) /* TX Status reg */
+ FIELD(TXSTATUS, TX_USED_BIT_READ_MIDFRAME, 12, 1)
+ FIELD(TXSTATUS, TX_FRAME_TOO_LARGE, 11, 1)
+ FIELD(TXSTATUS, TX_DMA_LOCKUP, 10, 1)
+ FIELD(TXSTATUS, TX_MAC_LOCKUP, 9, 1)
+ FIELD(TXSTATUS, RESP_NOT_OK, 8, 1)
+ FIELD(TXSTATUS, LATE_COLLISION, 7, 1)
+ FIELD(TXSTATUS, TRANSMIT_UNDER_RUN, 6, 1)
+ FIELD(TXSTATUS, TRANSMIT_COMPLETE, 5, 1)
+ FIELD(TXSTATUS, AMBA_ERROR, 4, 1)
+ FIELD(TXSTATUS, TRANSMIT_GO, 3, 1)
+ FIELD(TXSTATUS, RETRY_LIMIT, 2, 1)
+ FIELD(TXSTATUS, COLLISION, 1, 1)
+ FIELD(TXSTATUS, USED_BIT_READ, 0, 1)
+
REG32(RXQBASE, 0x18) /* RX Q Base address reg */
REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
REG32(RXSTATUS, 0x20) /* RX Status reg */
+ FIELD(RXSTATUS, RX_DMA_LOCKUP, 5, 1)
+ FIELD(RXSTATUS, RX_MAC_LOCKUP, 4, 1)
+ FIELD(RXSTATUS, RESP_NOT_OK, 3, 1)
+ FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1)
+ FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1)
+ FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
+
REG32(ISR, 0x24) /* Interrupt Status reg */
+ FIELD(ISR, TX_LOCKUP, 31, 1)
+ FIELD(ISR, RX_LOCKUP, 30, 1)
+ FIELD(ISR, TSU_TIMER, 29, 1)
+ FIELD(ISR, WOL, 28, 1)
+ FIELD(ISR, RECV_LPI, 27, 1)
+ FIELD(ISR, TSU_SEC_INCR, 26, 1)
+ FIELD(ISR, PTP_PDELAY_RESP_XMIT, 25, 1)
+ FIELD(ISR, PTP_PDELAY_REQ_XMIT, 24, 1)
+ FIELD(ISR, PTP_PDELAY_RESP_RECV, 23, 1)
+ FIELD(ISR, PTP_PDELAY_REQ_RECV, 22, 1)
+ FIELD(ISR, PTP_SYNC_XMIT, 21, 1)
+ FIELD(ISR, PTP_DELAY_REQ_XMIT, 20, 1)
+ FIELD(ISR, PTP_SYNC_RECV, 19, 1)
+ FIELD(ISR, PTP_DELAY_REQ_RECV, 18, 1)
+ FIELD(ISR, PCS_LP_PAGE_RECV, 17, 1)
+ FIELD(ISR, PCS_AN_COMPLETE, 16, 1)
+ FIELD(ISR, EXT_IRQ, 15, 1)
+ FIELD(ISR, PAUSE_FRAME_XMIT, 14, 1)
+ FIELD(ISR, PAUSE_TIME_ELAPSED, 13, 1)
+ FIELD(ISR, PAUSE_FRAME_RECV, 12, 1)
+ FIELD(ISR, RESP_NOT_OK, 11, 1)
+ FIELD(ISR, RECV_OVERRUN, 10, 1)
+ FIELD(ISR, LINK_CHANGE, 9, 1)
+ FIELD(ISR, USXGMII_INT, 8, 1)
+ FIELD(ISR, XMIT_COMPLETE, 7, 1)
+ FIELD(ISR, AMBA_ERROR, 6, 1)
+ FIELD(ISR, RETRY_EXCEEDED, 5, 1)
+ FIELD(ISR, XMIT_UNDER_RUN, 4, 1)
+ FIELD(ISR, TX_USED, 3, 1)
+ FIELD(ISR, RX_USED, 2, 1)
+ FIELD(ISR, RECV_COMPLETE, 1, 1)
+ FIELD(ISR, MGNT_FRAME_SENT, 0, 1)
REG32(IER, 0x28) /* Interrupt Enable reg */
REG32(IDR, 0x2c) /* Interrupt Disable reg */
REG32(IMR, 0x30) /* Interrupt Mask reg */
+
REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
+ FIELD(PHYMNTNC, DATA, 0, 16)
+ FIELD(PHYMNTNC, REG_ADDR, 18, 5)
+ FIELD(PHYMNTNC, PHY_ADDR, 23, 5)
+ FIELD(PHYMNTNC, OP, 28, 2)
+ FIELD(PHYMNTNC, ST, 30, 2)
+#define MDIO_OP_READ 0x3
+#define MDIO_OP_WRITE 0x2
+
REG32(RXPAUSE, 0x38) /* RX Pause Time reg */
REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */
REG32(SVLAN, 0xc0) /* Stacked VLAN reg */
REG32(MODID, 0xfc) /* Module ID reg */
-REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */
-REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */
+REG32(OCTTXLO, 0x100) /* Octets transmitted Low reg */
+REG32(OCTTXHI, 0x104) /* Octets transmitted High reg */
REG32(TXCNT, 0x108) /* Error-free Frames transmitted */
REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */
REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */
REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */
REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */
REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */
-REG32(OCTRXLO, 0x150) /* Octects Received register Low */
-REG32(OCTRXHI, 0x154) /* Octects Received register High */
+REG32(OCTRXLO, 0x150) /* Octets Received register Low */
+REG32(OCTRXHI, 0x154) /* Octets Received register High */
REG32(RXCNT, 0x158) /* Error-free Frames Received */
REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */
REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */
REG32(DESCONF4, 0x28c)
REG32(DESCONF5, 0x290)
REG32(DESCONF6, 0x294)
-#define GEM_DESCONF6_64B_MASK (1U << 23)
+ FIELD(DESCONF6, DMA_ADDR_64B, 23, 1)
REG32(DESCONF7, 0x298)
REG32(INT_Q1_STATUS, 0x400)
REG32(INT_Q7_DISABLE, 0x638)
REG32(SCREENING_TYPE1_REG0, 0x500)
-
-#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
-#define GEM_ST1R_DSTC_ENABLE (1 << 28)
-#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
-#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
-#define GEM_ST1R_DSTC_MATCH_SHIFT (4)
-#define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
-#define GEM_ST1R_QUEUE_SHIFT (0)
-#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
+ FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4)
+ FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8)
+ FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16)
+ FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1)
+ FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1)
+ FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1)
REG32(SCREENING_TYPE2_REG0, 0x540)
-
-#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
-#define GEM_ST2R_COMPARE_A_SHIFT (13)
-#define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
-#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
-#define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9)
-#define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
- + 1)
-#define GEM_ST2R_QUEUE_SHIFT (0)
-#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
+ FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4)
+ FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3)
+ FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1)
+ FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3)
+ FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1)
+ FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1)
REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0)
+
REG32(TYPE2_COMPARE_0_WORD_0, 0x700)
+ FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16)
+ FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16)
-#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
-#define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
-#define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
-#define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
+REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
+ FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7)
+ FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
+ FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
+ FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
/*****************************************/
-#define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
-#define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
-#define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
-#define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */
-
-#define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
-#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
-#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
-#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
-#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */
-#define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */
-#define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */
-#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
-#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
-#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */
-
-#define GEM_DMACFG_ADDR_64B (1U << 30)
-#define GEM_DMACFG_TX_BD_EXT (1U << 29)
-#define GEM_DMACFG_RX_BD_EXT (1U << 28)
-#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
-#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
-#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
-#define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
-
-#define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
-#define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */
-#define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
-#define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */
-/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
-#define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
-#define GEM_INT_AMBA_ERR 0x00000040
-#define GEM_INT_TXUSED 0x00000008
-#define GEM_INT_RXUSED 0x00000004
-#define GEM_INT_RXCMPL 0x00000002
-
-#define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
-#define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
-#define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
-#define GEM_PHYMNTNC_ADDR_SHFT 23
-#define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */
-#define GEM_PHYMNTNC_REG_SHIFT 18
/* Marvell PHY definitions */
#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */
{
uint64_t ret = desc[0];
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
ret |= (uint64_t)desc[2] << 32;
}
return ret;
{
uint64_t ret = desc[0] & ~0x3UL;
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
ret |= (uint64_t)desc[2] << 32;
}
return ret;
{
int ret = 2;
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
ret += 2;
}
- if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
- : GEM_DMACFG_TX_BD_EXT)) {
+ if (s->regs[R_DMACFG] & (rx_n_tx ? R_DMACFG_RX_BD_EXT_MODE_EN_MASK
+ : R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) {
ret += 2;
}
static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx)
{
uint32_t size;
- if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) {
size = s->regs[R_JUMBO_MAX_LEN];
if (size > s->jumbo_max_len) {
size = s->jumbo_max_len;
} else if (tx) {
size = 1518;
} else {
- size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
+ size = FIELD_EX32(s->regs[R_NWCFG],
+ NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518;
}
return size;
}
s = qemu_get_nic_opaque(nc);
/* Do nothing if receive is not enabled. */
- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) {
+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) {
if (s->can_rx_state != 1) {
s->can_rx_state = 1;
DB_PRINT("can't receive - no enable\n");
int i, is_mc;
/* Promiscuous mode? */
- if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) {
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) {
return GEM_RX_PROMISCUOUS_ACCEPT;
}
if (!memcmp(packet, broadcast_addr, 6)) {
/* Reject broadcast packets? */
- if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) {
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) {
return GEM_RX_REJECT;
}
return GEM_RX_BROADCAST_ACCEPT;
/* Accept packets -w- hash match? */
is_mc = is_multicast_ether_addr(packet);
- if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
- (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
+ if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) ||
+ (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) {
uint64_t buckets;
unsigned hash_index;
mismatched = false;
/* Screening is based on UDP Port */
- if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
+ if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) {
uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
- if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
- GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
+ if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) {
matched = true;
} else {
mismatched = true;
}
/* Screening is based on DS/TC */
- if (reg & GEM_ST1R_DSTC_ENABLE) {
+ if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) {
uint8_t dscp = rxbuf_ptr[14 + 1];
- if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
- GEM_ST1R_DSTC_MATCH_WIDTH)) {
+ if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) {
matched = true;
} else {
mismatched = true;
}
if (matched && !mismatched) {
- return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
+ return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM);
}
}
matched = false;
mismatched = false;
- if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
+ if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) {
uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
- int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
- GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
+ int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0,
+ ETHERTYPE_REG_INDEX);
if (et_idx > s->num_type2_screeners) {
qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
/* Compare A, B, C */
for (j = 0; j < 3; j++) {
- uint32_t cr0, cr1, mask;
+ uint32_t cr0, cr1, mask, compare;
uint16_t rx_cmp;
int offset;
- int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
- GEM_ST2R_COMPARE_WIDTH);
+ int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6,
+ R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH);
- if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
+ if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6,
+ R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) {
continue;
}
+
if (cr_idx > s->num_type2_screeners) {
qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
"register index: %d\n", cr_idx);
}
cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
- cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
- offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
- GEM_T2CW1_OFFSET_VALUE_WIDTH);
+ cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2];
+ offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE);
- switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
- GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
+ switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) {
case 3: /* Skip UDP header */
qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
"unimplemented - assuming UDP\n");
}
rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
- mask = extract32(cr0, 0, 16);
+ mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE);
+ compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE);
- if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
+ if ((rx_cmp & mask) == (compare & mask)) {
matched = true;
} else {
mismatched = true;
}
if (matched && !mismatched) {
- return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
+ return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM);
}
}
{
hwaddr desc_addr = 0;
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH];
}
desc_addr <<= 32;
/* Descriptor owned by software ? */
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
- s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
- gem_set_isr(s, q, GEM_INT_RXUSED);
+ s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
+ gem_set_isr(s, q, R_ISR_RX_USED_MASK);
/* Handle interrupt consequences */
gem_update_int_status(s);
}
}
/* Discard packets with receive length error enabled ? */
- if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) {
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) {
unsigned type_len;
/* Fish the ethertype / length field out of the RX packet */
/*
* Determine configured receive buffer offset (probably 0)
*/
- rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
- GEM_NWCFG_BUFF_OFST_S;
+ rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET);
/* The configure size of each receive buffer. Determines how many
* buffers needed to hold this packet.
*/
- rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
- GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
+ rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE);
+ rxbufsize *= GEM_DMACFG_RBUFSZ_MUL;
+
bytes_to_copy = size;
/* Hardware allows a zero value here but warns against it. To avoid QEMU
}
/* Strip of FCS field ? (usually yes) */
- if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) {
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
rxbuf_ptr = (void *)buf;
} else {
- unsigned crc_val;
+ uint32_t crc_val;
if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
size = MAX_FRAME_SIZE - sizeof(crc_val);
if (size > gem_get_max_buf_len(s, false)) {
qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n");
- gem_set_isr(s, q, GEM_INT_AMBA_ERR);
+ gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
return -1;
}
/* Count it */
gem_receive_updatestats(s, buf, size);
- s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
- gem_set_isr(s, q, GEM_INT_RXCMPL);
+ s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK;
+ gem_set_isr(s, q, R_ISR_RECV_COMPLETE_MASK);
/* Handle interrupt consequences */
gem_update_int_status(s);
int q = 0;
/* Do nothing if transmit is not enabled. */
- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) {
return;
}
while (tx_desc_get_used(desc) == 0) {
/* Do nothing if transmit is not enabled. */
- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) {
return;
}
print_gem_tx_desc(desc, q);
HWADDR_PRIx " too large: size 0x%x space 0x%zx\n",
packet_desc_addr, tx_desc_get_length(desc),
gem_get_max_buf_len(s, true) - (p - s->tx_packet));
- gem_set_isr(s, q, GEM_INT_AMBA_ERR);
+ gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
break;
}
}
DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
- s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
- gem_set_isr(s, q, GEM_INT_TXCMPL);
+ s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK;
+ gem_set_isr(s, q, R_ISR_XMIT_COMPLETE_MASK);
/* Handle interrupt consequences */
gem_update_int_status(s);
/* Is checksum offload enabled? */
- if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, TX_PBUF_CSUM_OFFLOAD)) {
net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL);
}
gem_transmit_updatestats(s, s->tx_packet, total_bytes);
/* Send the packet somewhere */
- if (s->phy_loop || (s->regs[R_NWCTRL] &
- GEM_NWCTRL_LOCALLOOP)) {
+ if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL,
+ LOOPBACK_LOCAL)) {
qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet,
total_bytes);
} else {
/* read next descriptor */
if (tx_desc_get_wrap(desc)) {
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
packet_desc_addr = s->regs[R_TBQPH];
packet_desc_addr <<= 32;
} else {
}
if (tx_desc_get_used(desc)) {
- s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED;
+ s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK;
/* IRQ TXUSED is defined only for queue 0 */
if (q == 0) {
- gem_set_isr(s, 0, GEM_INT_TXUSED);
+ gem_set_isr(s, 0, R_ISR_TX_USED_MASK);
}
gem_update_int_status(s);
}
s->regs[R_DESCONF] = 0x02D00111;
s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
s->regs[R_DESCONF5] = 0x002f2045;
- s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK;
+ s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK;
s->regs[R_INT_Q1_MASK] = 0x00000CE6;
s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len;
s->phy_regs[reg_num] = val;
}
+static void gem_handle_phy_access(CadenceGEMState *s)
+{
+ uint32_t val = s->regs[R_PHYMNTNC];
+ uint32_t phy_addr, reg_num;
+
+ phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
+
+ if (phy_addr != s->phy_addr) {
+ /* no phy at this address */
+ if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_READ) {
+ s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, 0xffff);
+ }
+ return;
+ }
+
+ reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
+
+ switch (FIELD_EX32(val, PHYMNTNC, OP)) {
+ case MDIO_OP_READ:
+ s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA,
+ gem_phy_read(s, reg_num));
+ break;
+
+ case MDIO_OP_WRITE:
+ gem_phy_write(s, reg_num, val);
+ break;
+
+ default:
+ break; /* only clause 22 operations are supported */
+ }
+}
+
/*
* gem_read32:
* Read a GEM register.
DB_PRINT("lowering irqs on ISR read\n");
/* The interrupts get updated at the end of the function. */
break;
- case R_PHYMNTNC:
- if (retval & GEM_PHYMNTNC_OP_R) {
- uint32_t phy_addr, reg_num;
-
- phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
- if (phy_addr == s->phy_addr) {
- reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
- retval &= 0xFFFF0000;
- retval |= gem_phy_read(s, reg_num);
- } else {
- retval |= 0xFFFF; /* No device at this address */
- }
- }
- break;
}
/* Squash read to clear bits */
/* Handle register write side effects */
switch (offset) {
case R_NWCTRL:
- if (val & GEM_NWCTRL_RXENA) {
+ if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) {
for (i = 0; i < s->num_priority_queues; ++i) {
gem_get_rx_desc(s, i);
}
}
- if (val & GEM_NWCTRL_TXSTART) {
+ if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) {
gem_transmit(s);
}
- if (!(val & GEM_NWCTRL_TXENA)) {
+ if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) {
/* Reset to start of Q when transmit disabled. */
for (i = 0; i < s->num_priority_queues; i++) {
s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i);
s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
break;
case R_PHYMNTNC:
- if (val & GEM_PHYMNTNC_OP_W) {
- uint32_t phy_addr, reg_num;
-
- phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
- if (phy_addr == s->phy_addr) {
- reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
- gem_phy_write(s, reg_num, val);
- }
- }
+ gem_handle_phy_access(s);
break;
}
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_gem_info, &s->conf,
- object_get_typename(OBJECT(dev)), dev->id, s);
+ object_get_typename(OBJECT(dev)), dev->id,
+ &dev->mem_reentrancy_guard, s);
if (s->jumbo_max_len > MAX_FRAME_SIZE) {
error_setg(errp, "jumbo-max-len is greater than %d",
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