NetClientState *nc;
} IGBTxPktVmdqCallbackContext;
+typedef struct L2Header {
+ struct eth_header eth;
+ struct vlan_header vlan[2];
+} L2Header;
+
+typedef struct PTP2 {
+ uint8_t message_id_transport_specific;
+ uint8_t version_ptp;
+ uint16_t message_length;
+ uint8_t subdomain_number;
+ uint8_t reserved0;
+ uint16_t flags;
+ uint64_t correction;
+ uint8_t reserved1[5];
+ uint8_t source_communication_technology;
+ uint32_t source_uuid_lo;
+ uint16_t source_uuid_hi;
+ uint16_t source_port_id;
+ uint16_t sequence_id;
+ uint8_t control;
+ uint8_t log_message_period;
+} PTP2;
+
static ssize_t
igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
bool has_vnet, bool *external_tx);
-static inline void
-igb_set_interrupt_cause(IGBCore *core, uint32_t val);
-
-static void igb_update_interrupt_state(IGBCore *core);
+static void igb_raise_interrupts(IGBCore *core, size_t index, uint32_t causes);
static void igb_reset(IGBCore *core, bool sw);
static inline void
pci_set_irq(core->owner, 0);
}
-static void igb_msix_notify(IGBCore *core, unsigned int vector)
+static void igb_msix_notify(IGBCore *core, unsigned int cause)
{
PCIDevice *dev = core->owner;
uint16_t vfn;
+ uint32_t effective_eiac;
+ unsigned int vector;
- vfn = 8 - (vector + 2) / IGBVF_MSIX_VEC_NUM;
+ vfn = 8 - (cause + 2) / IGBVF_MSIX_VEC_NUM;
if (vfn < pcie_sriov_num_vfs(core->owner)) {
dev = pcie_sriov_get_vf_at_index(core->owner, vfn);
assert(dev);
- vector = (vector + 2) % IGBVF_MSIX_VEC_NUM;
- } else if (vector >= IGB_MSIX_VEC_NUM) {
+ vector = (cause + 2) % IGBVF_MSIX_VEC_NUM;
+ } else if (cause >= IGB_MSIX_VEC_NUM) {
qemu_log_mask(LOG_GUEST_ERROR,
"igb: Tried to use vector unavailable for PF");
return;
+ } else {
+ vector = cause;
}
msix_notify(dev, vector);
+
+ trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]);
+ effective_eiac = core->mac[EIAC] & BIT(cause);
+ core->mac[EICR] &= ~effective_eiac;
}
static inline void
return E1000_MRQ_RSS_TYPE_IPV4TCP;
}
+ if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP &&
+ (core->mac[MRQC] & E1000_MRQC_RSS_FIELD_IPV4_UDP)) {
+ return E1000_MRQ_RSS_TYPE_IPV4UDP;
+ }
+
if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
return E1000_MRQ_RSS_TYPE_IPV4;
}
ip6info->rss_ex_dst_valid,
ip6info->rss_ex_src_valid,
core->mac[MRQC],
- E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]),
+ E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]),
E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
E1000_MRQC_EN_IPV6(core->mac[MRQC]));
ip6info->rss_ex_src_valid))) {
if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
- E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) {
- return E1000_MRQ_RSS_TYPE_IPV6TCP;
+ E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) {
+ return E1000_MRQ_RSS_TYPE_IPV6TCPEX;
+ }
+
+ if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP &&
+ (core->mac[MRQC] & E1000_MRQC_RSS_FIELD_IPV6_UDP)) {
+ return E1000_MRQ_RSS_TYPE_IPV6UDP;
}
if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
case E1000_MRQ_RSS_TYPE_IPV4TCP:
type = NetPktRssIpV4Tcp;
break;
- case E1000_MRQ_RSS_TYPE_IPV6TCP:
+ case E1000_MRQ_RSS_TYPE_IPV6TCPEX:
type = NetPktRssIpV6TcpEx;
break;
case E1000_MRQ_RSS_TYPE_IPV6:
case E1000_MRQ_RSS_TYPE_IPV6EX:
type = NetPktRssIpV6Ex;
break;
+ case E1000_MRQ_RSS_TYPE_IPV4UDP:
+ type = NetPktRssIpV4Udp;
+ break;
+ case E1000_MRQ_RSS_TYPE_IPV6UDP:
+ type = NetPktRssIpV6Udp;
+ break;
default:
assert(false);
return 0;
info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
}
+static void
+igb_tx_insert_vlan(IGBCore *core, uint16_t qn, struct igb_tx *tx,
+ uint16_t vlan, bool insert_vlan)
+{
+ if (core->mac[MRQC] & 1) {
+ uint16_t pool = qn % IGB_NUM_VM_POOLS;
+
+ if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_DEFAULT) {
+ /* always insert default VLAN */
+ insert_vlan = true;
+ vlan = core->mac[VMVIR0 + pool] & 0xffff;
+ } else if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_NEVER) {
+ insert_vlan = false;
+ }
+ }
+
+ if (insert_vlan) {
+ net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, vlan,
+ core->mac[VET] & 0xffff);
+ }
+}
+
static bool
igb_setup_tx_offloads(IGBCore *core, struct igb_tx *tx)
{
- if (tx->tse) {
- if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->mss)) {
+ uint32_t idx = (tx->first_olinfo_status >> 4) & 1;
+
+ if (tx->first_cmd_type_len & E1000_ADVTXD_DCMD_TSE) {
+ uint32_t mss = tx->ctx[idx].mss_l4len_idx >> E1000_ADVTXD_MSS_SHIFT;
+ if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, mss)) {
return false;
}
return true;
}
- if (tx->txsm) {
- if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) {
- return false;
- }
+ if ((tx->first_olinfo_status & E1000_ADVTXD_POTS_TXSM) &&
+ !((tx->ctx[idx].type_tucmd_mlhl & E1000_ADVTXD_TUCMD_L4T_SCTP) ?
+ net_tx_pkt_update_sctp_checksum(tx->tx_pkt) :
+ net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0))) {
+ return false;
}
- if (tx->ixsm) {
+ if (tx->first_olinfo_status & E1000_ADVTXD_POTS_IXSM) {
net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
}
}
static void
-igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt)
+igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt, int qn)
{
static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
PTC1023, PTC1522 };
g_assert_not_reached();
}
- core->mac[GPTC] = core->mac[TPT];
- core->mac[GOTCL] = core->mac[TOTL];
- core->mac[GOTCH] = core->mac[TOTH];
+ e1000x_inc_reg_if_not_full(core->mac, GPTC);
+ e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len);
+
+ if (core->mac[MRQC] & 1) {
+ uint16_t pool = qn % IGB_NUM_VM_POOLS;
+
+ core->mac[PVFGOTC0 + (pool * 64)] += tot_len;
+ core->mac[PVFGPTC0 + (pool * 64)]++;
+ }
}
static void
igb_process_tx_desc(IGBCore *core,
+ PCIDevice *dev,
struct igb_tx *tx,
union e1000_adv_tx_desc *tx_desc,
int queue_index)
{
struct e1000_adv_tx_context_desc *tx_ctx_desc;
uint32_t cmd_type_len;
- uint32_t olinfo_status;
+ uint32_t idx;
uint64_t buffer_addr;
uint16_t length;
E1000_ADVTXD_DTYP_DATA) {
/* advanced transmit data descriptor */
if (tx->first) {
- olinfo_status = le32_to_cpu(tx_desc->read.olinfo_status);
-
- tx->tse = !!(cmd_type_len & E1000_ADVTXD_DCMD_TSE);
- tx->ixsm = !!(olinfo_status & E1000_ADVTXD_POTS_IXSM);
- tx->txsm = !!(olinfo_status & E1000_ADVTXD_POTS_TXSM);
-
+ tx->first_cmd_type_len = cmd_type_len;
+ tx->first_olinfo_status = le32_to_cpu(tx_desc->read.olinfo_status);
tx->first = false;
}
} else if ((cmd_type_len & E1000_ADVTXD_DTYP_CTXT) ==
E1000_ADVTXD_DTYP_CTXT) {
/* advanced transmit context descriptor */
tx_ctx_desc = (struct e1000_adv_tx_context_desc *)tx_desc;
- tx->vlan = le32_to_cpu(tx_ctx_desc->vlan_macip_lens) >> 16;
- tx->mss = le32_to_cpu(tx_ctx_desc->mss_l4len_idx) >> 16;
+ idx = (le32_to_cpu(tx_ctx_desc->mss_l4len_idx) >> 4) & 1;
+ tx->ctx[idx].vlan_macip_lens = le32_to_cpu(tx_ctx_desc->vlan_macip_lens);
+ tx->ctx[idx].seqnum_seed = le32_to_cpu(tx_ctx_desc->seqnum_seed);
+ tx->ctx[idx].type_tucmd_mlhl = le32_to_cpu(tx_ctx_desc->type_tucmd_mlhl);
+ tx->ctx[idx].mss_l4len_idx = le32_to_cpu(tx_ctx_desc->mss_l4len_idx);
return;
} else {
/* unknown descriptor type */
length = cmd_type_len & 0xFFFF;
if (!tx->skip_cp) {
- if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, buffer_addr, length)) {
+ if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, dev,
+ buffer_addr, length)) {
tx->skip_cp = true;
}
}
if (cmd_type_len & E1000_TXD_CMD_EOP) {
if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
- if (cmd_type_len & E1000_TXD_CMD_VLE) {
- net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, tx->vlan,
- core->mac[VET] & 0xffff);
+ idx = (tx->first_olinfo_status >> 4) & 1;
+ igb_tx_insert_vlan(core, queue_index, tx,
+ tx->ctx[idx].vlan_macip_lens >> IGB_TX_FLAGS_VLAN_SHIFT,
+ !!(tx->first_cmd_type_len & E1000_TXD_CMD_VLE));
+
+ if ((tx->first_cmd_type_len & E1000_ADVTXD_MAC_TSTAMP) &&
+ (core->mac[TSYNCTXCTL] & E1000_TSYNCTXCTL_ENABLED) &&
+ !(core->mac[TSYNCTXCTL] & E1000_TSYNCTXCTL_VALID)) {
+ core->mac[TSYNCTXCTL] |= E1000_TSYNCTXCTL_VALID;
+ e1000x_timestamp(core->mac, core->timadj, TXSTMPL, TXSTMPH);
}
+
if (igb_tx_pkt_send(core, tx, queue_index)) {
- igb_on_tx_done_update_stats(core, tx->tx_pkt);
+ igb_on_tx_done_update_stats(core, tx->tx_pkt, queue_index);
}
}
tx->first = true;
tx->skip_cp = false;
- net_tx_pkt_reset(tx->tx_pkt);
+ net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, dev);
}
}
return igb_tx_wb_eic(core, txi->idx);
}
+static inline bool
+igb_tx_enabled(IGBCore *core, const E1000E_RingInfo *txi)
+{
+ bool vmdq = core->mac[MRQC] & 1;
+ uint16_t qn = txi->idx;
+ uint16_t pool = qn % IGB_NUM_VM_POOLS;
+
+ return (core->mac[TCTL] & E1000_TCTL_EN) &&
+ (!vmdq || core->mac[VFTE] & BIT(pool)) &&
+ (core->mac[TXDCTL0 + (qn * 16)] & E1000_TXDCTL_QUEUE_ENABLE);
+}
+
static void
igb_start_xmit(IGBCore *core, const IGB_TxRing *txr)
{
const E1000E_RingInfo *txi = txr->i;
uint32_t eic = 0;
- /* TODO: check if the queue itself is enabled too. */
- if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
+ if (!igb_tx_enabled(core, txi)) {
trace_e1000e_tx_disabled();
return;
}
trace_e1000e_tx_descr((void *)(intptr_t)desc.read.buffer_addr,
desc.read.cmd_type_len, desc.wb.status);
- igb_process_tx_desc(core, txr->tx, &desc, txi->idx);
+ igb_process_tx_desc(core, d, txr->tx, &desc, txi->idx);
igb_ring_advance(core, txi, 1);
eic |= igb_txdesc_writeback(core, base, &desc, txi);
}
if (eic) {
- core->mac[EICR] |= eic;
- igb_set_interrupt_cause(core, E1000_ICR_TXDW);
+ igb_raise_interrupts(core, EICR, eic);
+ igb_raise_interrupts(core, ICR, E1000_ICR_TXDW);
}
+
+ net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, d);
}
static uint32_t
for (i = 0; i < IGB_NUM_QUEUES; i++) {
E1000E_RxRing rxr;
+ if (!(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
+ continue;
+ }
igb_rx_ring_init(core, &rxr, i);
if (igb_ring_enabled(core, rxr.i) && igb_has_rxbufs(core, rxr.i, 1)) {
return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
}
-static uint16_t igb_receive_assign(IGBCore *core, const struct eth_header *ehdr,
- E1000E_RSSInfo *rss_info, bool *external_tx)
+static bool igb_rx_is_oversized(IGBCore *core, const struct eth_header *ehdr,
+ size_t size, size_t vlan_num,
+ bool lpe, uint16_t rlpml)
+{
+ size_t vlan_header_size = sizeof(struct vlan_header) * vlan_num;
+ size_t header_size = sizeof(struct eth_header) + vlan_header_size;
+ return lpe ? size + ETH_FCS_LEN > rlpml : size > header_size + ETH_MTU;
+}
+
+static uint16_t igb_receive_assign(IGBCore *core, const struct iovec *iov,
+ size_t iovcnt, size_t iov_ofs,
+ const L2Header *l2_header, size_t size,
+ E1000E_RSSInfo *rss_info,
+ uint16_t *etqf, bool *ts, bool *external_tx)
{
static const int ta_shift[] = { 4, 3, 2, 0 };
+ const struct eth_header *ehdr = &l2_header->eth;
uint32_t f, ra[2], *macp, rctl = core->mac[RCTL];
uint16_t queues = 0;
- uint16_t vid = lduw_be_p(&PKT_GET_VLAN_HDR(ehdr)->h_tci) & VLAN_VID_MASK;
- bool accepted = false;
+ uint16_t oversized = 0;
+ size_t vlan_num = 0;
+ PTP2 ptp2;
+ bool lpe;
+ uint16_t rlpml;
int i;
memset(rss_info, 0, sizeof(E1000E_RSSInfo));
+ *ts = false;
if (external_tx) {
*external_tx = true;
}
- if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff) &&
- e1000x_vlan_rx_filter_enabled(core->mac)) {
- uint32_t vfta =
- ldl_le_p((uint32_t *)(core->mac + VFTA) +
- ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK));
- if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) == 0) {
- trace_e1000e_rx_flt_vlan_mismatch(vid);
- return queues;
- } else {
- trace_e1000e_rx_flt_vlan_match(vid);
+ if (core->mac[CTRL_EXT] & BIT(26)) {
+ if (be16_to_cpu(ehdr->h_proto) == core->mac[VET] >> 16 &&
+ be16_to_cpu(l2_header->vlan[0].h_proto) == (core->mac[VET] & 0xffff)) {
+ vlan_num = 2;
+ }
+ } else {
+ if (be16_to_cpu(ehdr->h_proto) == (core->mac[VET] & 0xffff)) {
+ vlan_num = 1;
}
}
+ lpe = !!(core->mac[RCTL] & E1000_RCTL_LPE);
+ rlpml = core->mac[RLPML];
+ if (!(core->mac[RCTL] & E1000_RCTL_SBP) &&
+ igb_rx_is_oversized(core, ehdr, size, vlan_num, lpe, rlpml)) {
+ trace_e1000x_rx_oversized(size);
+ return queues;
+ }
+
+ for (*etqf = 0; *etqf < 8; (*etqf)++) {
+ if ((core->mac[ETQF0 + *etqf] & E1000_ETQF_FILTER_ENABLE) &&
+ be16_to_cpu(ehdr->h_proto) == (core->mac[ETQF0 + *etqf] & E1000_ETQF_ETYPE_MASK)) {
+ if ((core->mac[ETQF0 + *etqf] & E1000_ETQF_1588) &&
+ (core->mac[TSYNCRXCTL] & E1000_TSYNCRXCTL_ENABLED) &&
+ !(core->mac[TSYNCRXCTL] & E1000_TSYNCRXCTL_VALID) &&
+ iov_to_buf(iov, iovcnt, iov_ofs + ETH_HLEN, &ptp2, sizeof(ptp2)) >= sizeof(ptp2) &&
+ (ptp2.version_ptp & 15) == 2 &&
+ ptp2.message_id_transport_specific == ((core->mac[TSYNCRXCFG] >> 8) & 255)) {
+ e1000x_timestamp(core->mac, core->timadj, RXSTMPL, RXSTMPH);
+ *ts = true;
+ core->mac[TSYNCRXCTL] |= E1000_TSYNCRXCTL_VALID;
+ core->mac[RXSATRL] = le32_to_cpu(ptp2.source_uuid_lo);
+ core->mac[RXSATRH] = le16_to_cpu(ptp2.source_uuid_hi) |
+ (le16_to_cpu(ptp2.sequence_id) << 16);
+ }
+ break;
+ }
+ }
+
+ if (vlan_num &&
+ !e1000x_rx_vlan_filter(core->mac, l2_header->vlan + vlan_num - 1)) {
+ return queues;
+ }
+
if (core->mac[MRQC] & 1) {
if (is_broadcast_ether_addr(ehdr->h_dest)) {
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) {
queues |= BIT(i);
}
f = ta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
f = (((ehdr->h_dest[5] << 8) | ehdr->h_dest[4]) >> f) & 0xfff;
if (macp[f >> 5] & (1 << (f & 0x1f))) {
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) {
queues |= BIT(i);
}
if (e1000x_vlan_rx_filter_enabled(core->mac)) {
uint16_t mask = 0;
- if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff)) {
+ if (vlan_num) {
+ uint16_t vid = be16_to_cpu(l2_header->vlan[vlan_num - 1].h_tci) & VLAN_VID_MASK;
+
for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
if ((core->mac[VLVF0 + i] & E1000_VLVF_VLANID_MASK) == vid &&
(core->mac[VLVF0 + i] & E1000_VLVF_VLANID_ENABLE)) {
}
}
} else {
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) {
mask |= BIT(i);
}
queues = BIT(def_pl >> E1000_VT_CTL_DEFAULT_POOL_SHIFT);
}
- igb_rss_parse_packet(core, core->rx_pkt, external_tx != NULL, rss_info);
- if (rss_info->queue & 1) {
- queues <<= 8;
- }
- } else {
- switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
- case ETH_PKT_UCAST:
- if (rctl & E1000_RCTL_UPE) {
- accepted = true; /* promiscuous ucast */
- }
- break;
-
- case ETH_PKT_BCAST:
- if (rctl & E1000_RCTL_BAM) {
- accepted = true; /* broadcast enabled */
+ queues &= core->mac[VFRE];
+ if (queues) {
+ for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
+ lpe = !!(core->mac[VMOLR0 + i] & E1000_VMOLR_LPE);
+ rlpml = core->mac[VMOLR0 + i] & E1000_VMOLR_RLPML_MASK;
+ if ((queues & BIT(i)) &&
+ igb_rx_is_oversized(core, ehdr, size, vlan_num,
+ lpe, rlpml)) {
+ oversized |= BIT(i);
+ }
}
- break;
-
- case ETH_PKT_MCAST:
- if (rctl & E1000_RCTL_MPE) {
- accepted = true; /* promiscuous mcast */
+ /* 8.19.37 increment ROC if packet is oversized for all queues */
+ if (oversized == queues) {
+ trace_e1000x_rx_oversized(size);
+ e1000x_inc_reg_if_not_full(core->mac, ROC);
}
- break;
-
- default:
- g_assert_not_reached();
+ queues &= ~oversized;
}
- if (!accepted) {
- accepted = e1000x_rx_group_filter(core->mac, ehdr->h_dest);
+ if (queues) {
+ igb_rss_parse_packet(core, core->rx_pkt,
+ external_tx != NULL, rss_info);
+ /* Sec 8.26.1: PQn = VFn + VQn*8 */
+ if (rss_info->queue & 1) {
+ for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
+ if ((queues & BIT(i)) &&
+ (core->mac[VMOLR0 + i] & E1000_VMOLR_RSSE)) {
+ queues |= BIT(i + IGB_NUM_VM_POOLS);
+ queues &= ~BIT(i);
+ }
+ }
+ }
}
-
+ } else {
+ bool accepted = e1000x_rx_group_filter(core->mac, ehdr);
if (!accepted) {
for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) {
if (!(macp[1] & E1000_RAH_AV)) {
igb_build_rx_metadata(IGBCore *core,
struct NetRxPkt *pkt,
bool is_eop,
- const E1000E_RSSInfo *rss_info,
+ const E1000E_RSSInfo *rss_info, uint16_t etqf, bool ts,
uint16_t *pkt_info, uint16_t *hdr_info,
uint32_t *rss,
uint32_t *status_flags,
uint16_t *vlan_tag)
{
struct virtio_net_hdr *vhdr;
- bool hasip4, hasip6;
+ bool hasip4, hasip6, csum_valid;
EthL4HdrProto l4hdr_proto;
- uint32_t pkt_type;
*status_flags = E1000_RXD_STAT_DD;
trace_e1000e_rx_metadata_ack();
}
- if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
- trace_e1000e_rx_metadata_ipv6_filtering_disabled();
- pkt_type = E1000_RXD_PKT_MAC;
- } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP ||
- l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
- pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
- } else if (hasip4 || hasip6) {
- pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
- } else {
- pkt_type = E1000_RXD_PKT_MAC;
- }
+ if (pkt_info) {
+ *pkt_info = rss_info->enabled ? rss_info->type : 0;
- trace_e1000e_rx_metadata_pkt_type(pkt_type);
+ if (etqf < 8) {
+ *pkt_info |= (BIT(11) | etqf) << 4;
+ } else {
+ if (hasip4) {
+ *pkt_info |= E1000_ADVRXD_PKT_IP4;
+ }
- if (pkt_info) {
- if (rss_info->enabled) {
- *pkt_info = rss_info->type;
- }
+ if (hasip6) {
+ *pkt_info |= E1000_ADVRXD_PKT_IP6;
+ }
- *pkt_info |= (pkt_type << 4);
- } else {
- *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
+ switch (l4hdr_proto) {
+ case ETH_L4_HDR_PROTO_TCP:
+ *pkt_info |= E1000_ADVRXD_PKT_TCP;
+ break;
+
+ case ETH_L4_HDR_PROTO_UDP:
+ *pkt_info |= E1000_ADVRXD_PKT_UDP;
+ break;
+
+ case ETH_L4_HDR_PROTO_SCTP:
+ *pkt_info |= E1000_ADVRXD_PKT_SCTP;
+ break;
+
+ default:
+ break;
+ }
+ }
}
if (hdr_info) {
*hdr_info = 0;
}
+ if (ts) {
+ *status_flags |= BIT(16);
+ }
+
/* RX CSO information */
if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
trace_e1000e_rx_metadata_ipv6_sum_disabled();
if (igb_rx_l4_cso_enabled(core)) {
switch (l4hdr_proto) {
+ case ETH_L4_HDR_PROTO_SCTP:
+ if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
+ trace_e1000e_rx_metadata_l4_csum_validation_failed();
+ goto func_exit;
+ }
+ if (!csum_valid) {
+ *status_flags |= E1000_RXDEXT_STATERR_TCPE;
+ }
+ /* fall through */
case ETH_L4_HDR_PROTO_TCP:
*status_flags |= E1000_RXD_STAT_TCPCS;
break;
break;
default:
- goto func_exit;
+ break;
}
} else {
trace_e1000e_rx_metadata_l4_cso_disabled();
}
- trace_e1000e_rx_metadata_status_flags(*status_flags);
-
func_exit:
+ trace_e1000e_rx_metadata_status_flags(*status_flags);
*status_flags = cpu_to_le32(*status_flags);
}
static inline void
igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
struct NetRxPkt *pkt,
- const E1000E_RSSInfo *rss_info,
+ const E1000E_RSSInfo *rss_info, uint16_t etqf, bool ts,
uint16_t length)
{
uint32_t status_flags, rss;
desc->csum = 0;
igb_build_rx_metadata(core, pkt, pkt != NULL,
- rss_info,
+ rss_info, etqf, ts,
NULL, NULL, &rss,
&status_flags, &ip_id,
&desc->special);
static inline void
igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
struct NetRxPkt *pkt,
- const E1000E_RSSInfo *rss_info,
+ const E1000E_RSSInfo *rss_info, uint16_t etqf, bool ts,
uint16_t length)
{
memset(&desc->wb, 0, sizeof(desc->wb));
desc->wb.upper.length = cpu_to_le16(length);
igb_build_rx_metadata(core, pkt, pkt != NULL,
- rss_info,
+ rss_info, etqf, ts,
&desc->wb.lower.lo_dword.pkt_info,
&desc->wb.lower.lo_dword.hdr_info,
&desc->wb.lower.hi_dword.rss,
static inline void
igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
-struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length)
+ struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
+ uint16_t etqf, bool ts, uint16_t length)
{
if (igb_rx_use_legacy_descriptor(core)) {
- igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length);
+ igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info,
+ etqf, ts, length);
} else {
- igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info, length);
+ igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info,
+ etqf, ts, length);
}
}
}
static void
-igb_update_rx_stats(IGBCore *core, size_t data_size, size_t data_fcs_size)
+igb_update_rx_stats(IGBCore *core, const E1000E_RingInfo *rxi,
+ size_t pkt_size, size_t pkt_fcs_size)
{
- e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size);
+ eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt);
+ e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size);
- switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
- case ETH_PKT_BCAST:
- e1000x_inc_reg_if_not_full(core->mac, BPRC);
- break;
-
- case ETH_PKT_MCAST:
- e1000x_inc_reg_if_not_full(core->mac, MPRC);
- break;
+ if (core->mac[MRQC] & 1) {
+ uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS;
- default:
- break;
+ core->mac[PVFGORC0 + (pool * 64)] += pkt_size + 4;
+ core->mac[PVFGPRC0 + (pool * 64)]++;
+ if (pkt_type == ETH_PKT_MCAST) {
+ core->mac[PVFMPRC0 + (pool * 64)]++;
+ }
}
}
static void
igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt,
const E1000E_RxRing *rxr,
- const E1000E_RSSInfo *rss_info)
+ const E1000E_RSSInfo *rss_info,
+ uint16_t etqf, bool ts)
{
PCIDevice *d;
dma_addr_t base;
}
igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL,
- rss_info, written);
+ rss_info, etqf, ts, written);
igb_pci_dma_write_rx_desc(core, d, base, &desc, core->rx_desc_len);
igb_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
} while (desc_offset < total_size);
- igb_update_rx_stats(core, size, total_size);
+ igb_update_rx_stats(core, rxi, size, total_size);
+}
+
+static bool
+igb_rx_strip_vlan(IGBCore *core, const E1000E_RingInfo *rxi)
+{
+ if (core->mac[MRQC] & 1) {
+ uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS;
+ /* Sec 7.10.3.8: CTRL.VME is ignored, only VMOLR/RPLOLR is used */
+ return (net_rx_pkt_get_packet_type(core->rx_pkt) == ETH_PKT_MCAST) ?
+ core->mac[RPLOLR] & E1000_RPLOLR_STRVLAN :
+ core->mac[VMOLR0 + pool] & E1000_VMOLR_STRVLAN;
+ }
+
+ return e1000x_vlan_enabled(core->mac);
}
static inline void
igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
bool has_vnet, bool *external_tx)
{
- static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4);
-
uint16_t queues = 0;
- uint32_t n = 0;
- uint8_t min_buf[ETH_ZLEN];
+ uint32_t causes = 0;
+ uint32_t ecauses = 0;
+ union {
+ L2Header l2_header;
+ uint8_t octets[ETH_ZLEN];
+ } buf;
struct iovec min_iov;
- struct eth_header *ehdr;
- uint8_t *filter_buf;
size_t size, orig_size;
size_t iov_ofs = 0;
E1000E_RxRing rxr;
E1000E_RSSInfo rss_info;
+ uint16_t etqf;
+ bool ts;
size_t total_size;
+ int strip_vlan_index;
int i;
trace_e1000e_rx_receive_iov(iovcnt);
net_rx_pkt_unset_vhdr(core->rx_pkt);
}
- filter_buf = iov->iov_base + iov_ofs;
orig_size = iov_size(iov, iovcnt);
size = orig_size - iov_ofs;
/* Pad to minimum Ethernet frame length */
- if (size < sizeof(min_buf)) {
- iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size);
- memset(&min_buf[size], 0, sizeof(min_buf) - size);
+ if (size < sizeof(buf)) {
+ iov_to_buf(iov, iovcnt, iov_ofs, &buf, size);
+ memset(&buf.octets[size], 0, sizeof(buf) - size);
e1000x_inc_reg_if_not_full(core->mac, RUC);
- min_iov.iov_base = filter_buf = min_buf;
- min_iov.iov_len = size = sizeof(min_buf);
+ min_iov.iov_base = &buf;
+ min_iov.iov_len = size = sizeof(buf);
iovcnt = 1;
iov = &min_iov;
iov_ofs = 0;
- } else if (iov->iov_len < maximum_ethernet_hdr_len) {
- /* This is very unlikely, but may happen. */
- iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len);
- filter_buf = min_buf;
- }
-
- /* Discard oversized packets if !LPE and !SBP. */
- if (e1000x_is_oversized(core->mac, size)) {
- return orig_size;
+ } else {
+ iov_to_buf(iov, iovcnt, iov_ofs, &buf, sizeof(buf.l2_header));
}
- ehdr = PKT_GET_ETH_HDR(filter_buf);
- net_rx_pkt_set_packet_type(core->rx_pkt, get_eth_packet_type(ehdr));
-
- net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
- e1000x_vlan_enabled(core->mac),
- core->mac[VET] & 0xffff);
+ net_rx_pkt_set_packet_type(core->rx_pkt,
+ get_eth_packet_type(&buf.l2_header.eth));
+ net_rx_pkt_set_protocols(core->rx_pkt, iov, iovcnt, iov_ofs);
- queues = igb_receive_assign(core, ehdr, &rss_info, external_tx);
+ queues = igb_receive_assign(core, iov, iovcnt, iov_ofs,
+ &buf.l2_header, size,
+ &rss_info, &etqf, &ts, external_tx);
if (!queues) {
trace_e1000e_rx_flt_dropped();
return orig_size;
}
- total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
- e1000x_fcs_len(core->mac);
-
for (i = 0; i < IGB_NUM_QUEUES; i++) {
- if (!(queues & BIT(i))) {
+ if (!(queues & BIT(i)) ||
+ !(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
continue;
}
igb_rx_ring_init(core, &rxr, i);
+ if (!igb_rx_strip_vlan(core, rxr.i)) {
+ strip_vlan_index = -1;
+ } else if (core->mac[CTRL_EXT] & BIT(26)) {
+ strip_vlan_index = 1;
+ } else {
+ strip_vlan_index = 0;
+ }
+
+ net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
+ strip_vlan_index,
+ core->mac[VET] & 0xffff,
+ core->mac[VET] >> 16);
+
+ total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
+ e1000x_fcs_len(core->mac);
+
if (!igb_has_rxbufs(core, rxr.i, total_size)) {
- n |= E1000_ICS_RXO;
+ causes |= E1000_ICS_RXO;
trace_e1000e_rx_not_written_to_guest(rxr.i->idx);
continue;
}
- n |= E1000_ICR_RXT0;
+ causes |= E1000_ICR_RXDW;
igb_rx_fix_l4_csum(core, core->rx_pkt);
- igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
+ igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info, etqf, ts);
/* Check if receive descriptor minimum threshold hit */
if (igb_rx_descr_threshold_hit(core, rxr.i)) {
- n |= E1000_ICS_RXDMT0;
+ causes |= E1000_ICS_RXDMT0;
}
- core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
+ ecauses |= igb_rx_wb_eic(core, rxr.i->idx);
trace_e1000e_rx_written_to_guest(rxr.i->idx);
}
- trace_e1000e_rx_interrupt_set(n);
- igb_set_interrupt_cause(core, n);
+ trace_e1000e_rx_interrupt_set(causes);
+ igb_raise_interrupts(core, EICR, ecauses);
+ igb_raise_interrupts(core, ICR, causes);
return orig_size;
}
}
if (core->mac[STATUS] != old_status) {
- igb_set_interrupt_cause(core, E1000_ICR_LSC);
+ igb_raise_interrupts(core, ICR, E1000_ICR_LSC);
}
}
}
}
-static inline void
-igb_clear_ims_bits(IGBCore *core, uint32_t bits)
-{
- trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
- core->mac[IMS] &= ~bits;
-}
-
static inline bool
igb_postpone_interrupt(IGBIntrDelayTimer *timer)
{
return igb_postpone_interrupt(&core->eitr[idx]);
}
-static void igb_send_msix(IGBCore *core)
+static void igb_send_msix(IGBCore *core, uint32_t causes)
{
- uint32_t causes = core->mac[EICR] & core->mac[EIMS];
- uint32_t effective_eiac;
int vector;
for (vector = 0; vector < IGB_INTR_NUM; ++vector) {
trace_e1000e_irq_msix_notify_vec(vector);
igb_msix_notify(core, vector);
-
- trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]);
- effective_eiac = core->mac[EIAC] & BIT(vector);
- core->mac[EICR] &= ~effective_eiac;
}
}
}
trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
}
-static void
-igb_update_interrupt_state(IGBCore *core)
+static void igb_raise_interrupts(IGBCore *core, size_t index, uint32_t causes)
{
- uint32_t icr;
- uint32_t causes;
+ uint32_t old_causes = core->mac[ICR] & core->mac[IMS];
+ uint32_t old_ecauses = core->mac[EICR] & core->mac[EIMS];
+ uint32_t raised_causes;
+ uint32_t raised_ecauses;
uint32_t int_alloc;
- icr = core->mac[ICR] & core->mac[IMS];
+ trace_e1000e_irq_set(index << 2,
+ core->mac[index], core->mac[index] | causes);
- if (msix_enabled(core->owner)) {
- if (icr) {
- causes = 0;
- if (icr & E1000_ICR_DRSTA) {
- int_alloc = core->mac[IVAR_MISC] & 0xff;
- if (int_alloc & E1000_IVAR_VALID) {
- causes |= BIT(int_alloc & 0x1f);
- }
+ core->mac[index] |= causes;
+
+ if (core->mac[GPIE] & E1000_GPIE_MSIX_MODE) {
+ raised_causes = core->mac[ICR] & core->mac[IMS] & ~old_causes;
+
+ if (raised_causes & E1000_ICR_DRSTA) {
+ int_alloc = core->mac[IVAR_MISC] & 0xff;
+ if (int_alloc & E1000_IVAR_VALID) {
+ core->mac[EICR] |= BIT(int_alloc & 0x1f);
}
- /* Check if other bits (excluding the TCP Timer) are enabled. */
- if (icr & ~E1000_ICR_DRSTA) {
- int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff;
- if (int_alloc & E1000_IVAR_VALID) {
- causes |= BIT(int_alloc & 0x1f);
- }
- trace_e1000e_irq_add_msi_other(core->mac[EICR]);
+ }
+ /* Check if other bits (excluding the TCP Timer) are enabled. */
+ if (raised_causes & ~E1000_ICR_DRSTA) {
+ int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff;
+ if (int_alloc & E1000_IVAR_VALID) {
+ core->mac[EICR] |= BIT(int_alloc & 0x1f);
}
- core->mac[EICR] |= causes;
}
- if ((core->mac[EICR] & core->mac[EIMS])) {
- igb_send_msix(core);
+ raised_ecauses = core->mac[EICR] & core->mac[EIMS] & ~old_ecauses;
+ if (!raised_ecauses) {
+ return;
}
+
+ igb_send_msix(core, raised_ecauses);
} else {
igb_fix_icr_asserted(core);
- if (icr) {
- core->mac[EICR] |= (icr & E1000_ICR_DRSTA) | E1000_EICR_OTHER;
- } else {
- core->mac[EICR] &= ~E1000_EICR_OTHER;
+ raised_causes = core->mac[ICR] & core->mac[IMS] & ~old_causes;
+ if (!raised_causes) {
+ return;
}
- trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
- core->mac[ICR], core->mac[IMS]);
+ core->mac[EICR] |= (raised_causes & E1000_ICR_DRSTA) | E1000_EICR_OTHER;
- if (msi_enabled(core->owner)) {
- if (icr) {
- msi_notify(core->owner, 0);
- }
+ if (msix_enabled(core->owner)) {
+ trace_e1000e_irq_msix_notify_vec(0);
+ msix_notify(core->owner, 0);
+ } else if (msi_enabled(core->owner)) {
+ trace_e1000e_irq_msi_notify(raised_causes);
+ msi_notify(core->owner, 0);
} else {
- if (icr) {
- igb_raise_legacy_irq(core);
- } else {
- igb_lower_legacy_irq(core);
- }
+ igb_raise_legacy_irq(core);
}
}
}
-static void
-igb_set_interrupt_cause(IGBCore *core, uint32_t val)
+static void igb_lower_interrupts(IGBCore *core, size_t index, uint32_t causes)
{
- trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
+ trace_e1000e_irq_clear(index << 2,
+ core->mac[index], core->mac[index] & ~causes);
- core->mac[ICR] |= val;
+ core->mac[index] &= ~causes;
- trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
+ trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
+ core->mac[ICR], core->mac[IMS]);
- igb_update_interrupt_state(core);
+ if (!(core->mac[ICR] & core->mac[IMS]) &&
+ !(core->mac[GPIE] & E1000_GPIE_MSIX_MODE)) {
+ core->mac[EICR] &= ~E1000_EICR_OTHER;
+
+ if (!msix_enabled(core->owner) && !msi_enabled(core->owner)) {
+ igb_lower_legacy_irq(core);
+ }
+ }
}
static void igb_set_eics(IGBCore *core, int index, uint32_t val)
{
bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
+ uint32_t mask = msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK;
trace_igb_irq_write_eics(val, msix);
-
- core->mac[EICS] |=
- val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK);
-
- /*
- * TODO: Move to igb_update_interrupt_state if EICS is modified in other
- * places.
- */
- core->mac[EICR] = core->mac[EICS];
-
- igb_update_interrupt_state(core);
+ igb_raise_interrupts(core, EICR, val & mask);
}
static void igb_set_eims(IGBCore *core, int index, uint32_t val)
{
bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
+ uint32_t mask = msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK;
trace_igb_irq_write_eims(val, msix);
-
- core->mac[EIMS] |=
- val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK);
-
- igb_update_interrupt_state(core);
-}
-
-static void igb_vf_reset(IGBCore *core, uint16_t vfn)
-{
- /* TODO: Reset of the queue enable and the interrupt registers of the VF. */
-
- core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI;
- core->mac[V2PMAILBOX0 + vfn] = E1000_V2PMAILBOX_RSTD;
+ igb_raise_interrupts(core, EIMS, val & mask);
}
static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn)
{
uint32_t ent = core->mac[VTIVAR_MISC + vfn];
+ uint32_t causes;
if ((ent & E1000_IVAR_VALID)) {
- core->mac[EICR] |= (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM);
- igb_update_interrupt_state(core);
+ causes = (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM);
+ igb_raise_interrupts(core, EICR, causes);
}
}
static void mailbox_interrupt_to_pf(IGBCore *core)
{
- igb_set_interrupt_cause(core, E1000_ICR_VMMB);
+ igb_raise_interrupts(core, ICR, E1000_ICR_VMMB);
}
static void igb_set_pfmailbox(IGBCore *core, int index, uint32_t val)
}
}
+static void igb_vf_reset(IGBCore *core, uint16_t vfn)
+{
+ uint16_t qn0 = vfn;
+ uint16_t qn1 = vfn + IGB_NUM_VM_POOLS;
+
+ /* disable Rx and Tx for the VF*/
+ core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
+ core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
+ core->mac[TXDCTL0 + (qn0 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
+ core->mac[TXDCTL0 + (qn1 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
+ core->mac[VFRE] &= ~BIT(vfn);
+ core->mac[VFTE] &= ~BIT(vfn);
+ /* indicate VF reset to PF */
+ core->mac[VFLRE] |= BIT(vfn);
+ /* VFLRE and mailbox use the same interrupt cause */
+ mailbox_interrupt_to_pf(core);
+}
+
static void igb_w1c(IGBCore *core, int index, uint32_t val)
{
core->mac[index] &= ~val;
static void igb_set_eimc(IGBCore *core, int index, uint32_t val)
{
bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
+ uint32_t mask = msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK;
- /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */
- core->mac[EIMS] &=
- ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
+ trace_igb_irq_write_eimc(val, msix);
- trace_igb_irq_write_eimc(val, core->mac[EIMS], msix);
- igb_update_interrupt_state(core);
+ /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */
+ igb_lower_interrupts(core, EIMS, val & mask);
}
static void igb_set_eiac(IGBCore *core, int index, uint32_t val)
* TODO: In IOV mode, only bit zero of this vector is available for the PF
* function.
*/
- core->mac[EICR] &=
- ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
+ uint32_t mask = msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK;
trace_igb_irq_write_eicr(val, msix);
- igb_update_interrupt_state(core);
+ igb_lower_interrupts(core, EICR, val & mask);
}
static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val)
igb_update_flowctl_status(core);
/* signal link status change to the guest */
- igb_set_interrupt_cause(core, E1000_ICR_LSC);
+ igb_raise_interrupts(core, ICR, E1000_ICR_LSC);
}
}
core->mac[MDIC] = val | E1000_MDIC_READY;
if (val & E1000_MDIC_INT_EN) {
- igb_set_interrupt_cause(core, E1000_ICR_MDAC);
+ igb_raise_interrupts(core, ICR, E1000_ICR_MDAC);
}
}
static void
igb_set_ctrlext(IGBCore *core, int index, uint32_t val)
{
- trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
- !!(val & E1000_CTRL_EXT_SPD_BYPS));
-
- /* TODO: PFRSTD */
+ trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
+ !!(val & E1000_CTRL_EXT_SPD_BYPS),
+ !!(val & E1000_CTRL_EXT_PFRSTD));
/* Zero self-clearing bits */
val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
core->mac[CTRL_EXT] = val;
+
+ if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) {
+ for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
+ core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI;
+ core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD;
+ }
+ }
}
static void
igb_set_ics(IGBCore *core, int index, uint32_t val)
{
trace_e1000e_irq_write_ics(val);
- igb_set_interrupt_cause(core, val);
+ igb_raise_interrupts(core, ICR, val);
}
static void
igb_set_imc(IGBCore *core, int index, uint32_t val)
{
trace_e1000e_irq_ims_clear_set_imc(val);
- igb_clear_ims_bits(core, val);
- igb_update_interrupt_state(core);
+ igb_lower_interrupts(core, IMS, val);
}
static void
igb_set_ims(IGBCore *core, int index, uint32_t val)
{
- uint32_t valid_val = val & 0x77D4FBFD;
-
- trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
- core->mac[IMS] |= valid_val;
- igb_update_interrupt_state(core);
+ igb_raise_interrupts(core, IMS, val & 0x77D4FBFD);
}
-static void igb_commit_icr(IGBCore *core)
+static void igb_nsicr(IGBCore *core)
{
/*
- * If GPIE.NSICR = 0, then the copy of IAM to IMS will occur only if at
+ * If GPIE.NSICR = 0, then the clear of IMS will occur only if at
* least one bit is set in the IMS and there is a true interrupt as
* reflected in ICR.INTA.
*/
if ((core->mac[GPIE] & E1000_GPIE_NSICR) ||
(core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) {
- igb_set_ims(core, IMS, core->mac[IAM]);
- } else {
- igb_update_interrupt_state(core);
+ igb_lower_interrupts(core, IMS, core->mac[IAM]);
}
}
static void igb_set_icr(IGBCore *core, int index, uint32_t val)
{
- uint32_t icr = core->mac[ICR] & ~val;
-
- trace_igb_irq_icr_write(val, core->mac[ICR], icr);
- core->mac[ICR] = icr;
- igb_commit_icr(core);
+ igb_nsicr(core);
+ igb_lower_interrupts(core, ICR, val);
}
static uint32_t
igb_mac_icr_read(IGBCore *core, int index)
{
uint32_t ret = core->mac[ICR];
- trace_e1000e_irq_icr_read_entry(ret);
if (core->mac[GPIE] & E1000_GPIE_NSICR) {
trace_igb_irq_icr_clear_gpie_nsicr();
- core->mac[ICR] = 0;
+ igb_lower_interrupts(core, ICR, 0xffffffff);
} else if (core->mac[IMS] == 0) {
trace_e1000e_irq_icr_clear_zero_ims();
- core->mac[ICR] = 0;
+ igb_lower_interrupts(core, ICR, 0xffffffff);
+ } else if (core->mac[ICR] & E1000_ICR_INT_ASSERTED) {
+ igb_lower_interrupts(core, ICR, 0xffffffff);
} else if (!msix_enabled(core->owner)) {
trace_e1000e_irq_icr_clear_nonmsix_icr_read();
- core->mac[ICR] = 0;
+ igb_lower_interrupts(core, ICR, 0xffffffff);
}
- trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
- igb_commit_icr(core);
+ igb_nsicr(core);
return ret;
}
res |= E1000_STATUS_IOV_MODE;
}
- /*
- * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is
- * left set after E1000_CTRL_LRST is set.
- */
- if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE) &&
- !(core->mac[CTRL] & E1000_CTRL_LRST)) {
+ if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
res |= E1000_STATUS_GIO_MASTER_ENABLE;
}
[EIAM] = igb_mac_readreg,
[IVAR0 ... IVAR0 + 7] = igb_mac_readreg,
igb_getreg(IVAR_MISC),
+ igb_getreg(TSYNCRXCFG),
+ [ETQF0 ... ETQF0 + 7] = igb_mac_readreg,
igb_getreg(VT_CTL),
[P2VMAILBOX0 ... P2VMAILBOX7] = igb_mac_readreg,
[V2PMAILBOX0 ... V2PMAILBOX7] = igb_mac_vfmailbox_read,
[EIMS] = igb_set_eims,
[IVAR0 ... IVAR0 + 7] = igb_mac_writereg,
igb_putreg(IVAR_MISC),
+ igb_putreg(TSYNCRXCFG),
+ [ETQF0 ... ETQF0 + 7] = igb_mac_writereg,
igb_putreg(VT_CTL),
[P2VMAILBOX0 ... P2VMAILBOX7] = igb_set_pfmailbox,
[V2PMAILBOX0 ... V2PMAILBOX7] = igb_set_vfmailbox,
core->vmstate = qemu_add_vm_change_state_handler(igb_vm_state_change, core);
for (i = 0; i < IGB_NUM_QUEUES; i++) {
- net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner, E1000E_MAX_TX_FRAGS);
+ net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS);
}
net_rx_pkt_init(&core->rx_pkt);
qemu_del_vm_change_state_handler(core->vmstate);
for (i = 0; i < IGB_NUM_QUEUES; i++) {
- net_tx_pkt_reset(core->tx[i].tx_pkt);
net_tx_pkt_uninit(core->tx[i].tx_pkt);
}
static const uint32_t igb_mac_reg_init[] = {
[LEDCTL] = 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24),
[EEMNGCTL] = BIT(31),
+ [TXDCTL0] = E1000_TXDCTL_QUEUE_ENABLE,
[RXDCTL0] = E1000_RXDCTL_QUEUE_ENABLE | (1 << 16),
[RXDCTL1] = 1 << 16,
[RXDCTL2] = 1 << 16,
[VMOLR0 ... VMOLR0 + 7] = 0x2600 | E1000_VMOLR_STRCRC,
[RPLOLR] = E1000_RPLOLR_STRCRC,
[RLPML] = 0x2600,
- [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
- [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN |
- E1000_DCA_TXCTRL_TX_WB_RO_EN |
- E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
+ [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN |
+ E1000_DCA_TXCTRL_TX_WB_RO_EN |
+ E1000_DCA_TXCTRL_DESC_RRO_EN,
};
static void igb_reset(IGBCore *core, bool sw)
e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
+ for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
+ /* Set RSTI, so VF can identify a PF reset is in progress */
+ core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI;
+ }
+
for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
tx = &core->tx[i];
- net_tx_pkt_reset(tx->tx_pkt);
- tx->vlan = 0;
- tx->mss = 0;
- tx->tse = false;
- tx->ixsm = false;
- tx->txsm = false;
+ memset(tx->ctx, 0, sizeof(tx->ctx));
tx->first = true;
tx->skip_cp = false;
}
projects / mirror_qemu.git / blobdiff