case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
+ /* fall through */
case 0x10: /* DMA4_IRQSTATUS_L2 */
irqn ++;
+ /* fall through */
case 0x0c: /* DMA4_IRQSTATUS_L1 */
irqn ++;
+ /* fall through */
case 0x08: /* DMA4_IRQSTATUS_L0 */
return s->irqstat[irqn];
case 0x24: /* DMA4_IRQENABLE_L3 */
irqn ++;
+ /* fall through */
case 0x20: /* DMA4_IRQENABLE_L2 */
irqn ++;
+ /* fall through */
case 0x1c: /* DMA4_IRQENABLE_L1 */
irqn ++;
+ /* fall through */
case 0x18: /* DMA4_IRQENABLE_L0 */
return s->irqen[irqn];
switch (addr) {
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
+ /* fall through */
case 0x10: /* DMA4_IRQSTATUS_L2 */
irqn ++;
+ /* fall through */
case 0x0c: /* DMA4_IRQSTATUS_L1 */
irqn ++;
+ /* fall through */
case 0x08: /* DMA4_IRQSTATUS_L0 */
s->irqstat[irqn] &= ~value;
if (!s->irqstat[irqn])
case 0x24: /* DMA4_IRQENABLE_L3 */
irqn ++;
+ /* fall through */
case 0x20: /* DMA4_IRQENABLE_L2 */
irqn ++;
+ /* fall through */
case 0x1c: /* DMA4_IRQENABLE_L1 */
irqn ++;
+ /* fall through */
case 0x18: /* DMA4_IRQENABLE_L0 */
s->irqen[irqn] = value;
return;