*/
#include "qemu/osdep.h"
-#include "hw/hw.h"
+#include "qemu-common.h"
+#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_host.h"
+#include "hw/qdev-properties.h"
+#include "migration/qemu-file-types.h"
+#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "net/net.h"
+#include "sysemu/numa.h"
#include "sysemu/sysemu.h"
#include "hw/loader.h"
#include "qemu/error-report.h"
DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
- DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
- QEMU_PCI_CAP_SERR_BITNR, true),
DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
QEMU_PCIE_EXTCAP_INIT_BITNR, true),
+ DEFINE_PROP_STRING("failover_pair_id", PCIDevice,
+ failover_pair_id),
DEFINE_PROP_END_OF_LIST()
};
vmstate_register(NULL, -1, &vmstate_pcibus, bus);
}
-static void pci_bus_unrealize(BusState *qbus, Error **errp)
+static void pcie_bus_realize(BusState *qbus, Error **errp)
{
PCIBus *bus = PCI_BUS(qbus);
- qemu_remove_machine_init_done_notifier(&bus->machine_done);
+ pci_bus_realize(qbus, errp);
- vmstate_unregister(NULL, &vmstate_pcibus, bus);
+ /*
+ * A PCI-E bus can support extended config space if it's the root
+ * bus, or if the bus/bridge above it does as well
+ */
+ if (pci_bus_is_root(bus)) {
+ bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
+ } else {
+ PCIBus *parent_bus = pci_get_bus(bus->parent_dev);
+
+ if (pci_bus_allows_extended_config_space(parent_bus)) {
+ bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
+ }
+ }
}
-static bool pcibus_is_root(PCIBus *bus)
+static void pci_bus_unrealize(BusState *qbus, Error **errp)
{
- return !bus->parent_dev;
+ PCIBus *bus = PCI_BUS(qbus);
+
+ qemu_remove_machine_init_done_notifier(&bus->machine_done);
+
+ vmstate_unregister(NULL, &vmstate_pcibus, bus);
}
static int pcibus_num(PCIBus *bus)
{
- if (pcibus_is_root(bus)) {
+ if (pci_bus_is_root(bus)) {
return 0; /* pci host bridge */
}
return bus->parent_dev->config[PCI_SECONDARY_BUS];
return NUMA_NODE_UNASSIGNED;
}
-static bool pcibus_allows_extended_config_space(PCIBus *bus)
-{
- return false;
-}
-
static void pci_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
k->unrealize = pci_bus_unrealize;
k->reset = pcibus_reset;
- pbc->is_root = pcibus_is_root;
pbc->bus_num = pcibus_num;
pbc->numa_node = pcibus_numa_node;
- pbc->allows_extended_config_space = pcibus_allows_extended_config_space;
}
static const TypeInfo pci_bus_info = {
.parent = TYPE_INTERFACE,
};
-static bool pciebus_allows_extended_config_space(PCIBus *bus)
-{
- return true;
-}
-
static void pcie_bus_class_init(ObjectClass *klass, void *data)
{
- PCIBusClass *pbc = PCI_BUS_CLASS(klass);
+ BusClass *k = BUS_CLASS(klass);
- pbc->allows_extended_config_space = pciebus_allows_extended_config_space;
+ k->realize = pcie_bus_realize;
}
static const TypeInfo pcie_bus_info = {
bus->slot_reserved_mask = 0x0;
bus->address_space_mem = address_space_mem;
bus->address_space_io = address_space_io;
+ bus->flags |= PCI_BUS_IS_ROOT;
/* host bridge */
QLIST_INIT(&bus->child);
return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
}
-bool pci_bus_is_root(PCIBus *bus)
-{
- return PCI_BUS_GET_CLASS(bus)->is_root(bus);
-}
-
-bool pci_bus_allows_extended_config_space(PCIBus *bus)
-{
- return PCI_BUS_GET_CLASS(bus)->allows_extended_config_space(bus);
-}
-
void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
const char *name,
MemoryRegion *address_space_mem,
return 0;
}
-static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
- const char *devaddr)
-{
- int dom, bus;
- unsigned slot;
-
- if (!root) {
- fprintf(stderr, "No primary PCI bus\n");
- return NULL;
- }
-
- assert(!root->parent_dev);
-
- if (!devaddr) {
- *devfnp = -1;
- return pci_find_bus_nr(root, 0);
- }
-
- if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
- return NULL;
- }
-
- if (dom != 0) {
- fprintf(stderr, "No support for non-zero PCI domains\n");
- return NULL;
- }
-
- *devfnp = PCI_DEVFN(slot, 0);
- return pci_find_bus_nr(root, bus);
-}
-
static void pci_init_cmask(PCIDevice *dev)
{
pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
pci_set_word(dev->wmask + PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_INTX_DISABLE);
- if (dev->cap_present & QEMU_PCI_CAP_SERR) {
- pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
- }
+ pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
config_size - PCI_CONFIG_HEADER_SIZE);
result = PCI_BUILD_BDF(bus_n, 0);
break;
default:
- error_printf("Invalid PCI requester ID cache type: %d\n",
+ error_report("Invalid PCI requester ID cache type: %d",
cache->type);
exit(1);
break;
*/
int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
{
- return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
+ return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin);
}
/***********************************************************/
DeviceState *dev;
int devfn;
int i;
+ int dom, busnr;
+ unsigned slot;
if (nd->model && !strcmp(nd->model, "virtio")) {
g_free(nd->model);
exit(1);
}
- bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
+ if (!rootbus) {
+ error_report("No primary PCI bus");
+ exit(1);
+ }
+
+ assert(!rootbus->parent_dev);
+
+ if (!devaddr) {
+ devfn = -1;
+ busnr = 0;
+ } else {
+ if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) {
+ error_report("Invalid PCI device address %s for device %s",
+ devaddr, nd->model);
+ exit(1);
+ }
+
+ if (dom != 0) {
+ error_report("No support for non-zero PCI domains");
+ exit(1);
+ }
+
+ devfn = PCI_DEVFN(slot, 0);
+ }
+
+ bus = pci_find_bus_nr(rootbus, busnr);
if (!bus) {
error_report("Invalid PCI device address %s for device %s",
devaddr, nd->model);
ObjectClass *klass = OBJECT_CLASS(pc);
Error *local_err = NULL;
bool is_default_rom;
+ uint16_t class_id;
/* initialize cap_present for pci_is_express() and pci_config_size(),
* Note that hybrid PCIs are not set automatically and need to manage
}
}
+ if (pci_dev->failover_pair_id) {
+ if (!pci_bus_is_express(pci_get_bus(pci_dev))) {
+ error_setg(errp, "failover primary device must be on "
+ "PCIExpress bus");
+ error_propagate(errp, local_err);
+ pci_qdev_unrealize(DEVICE(pci_dev), NULL);
+ return;
+ }
+ class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE);
+ if (class_id != PCI_CLASS_NETWORK_ETHERNET) {
+ error_setg(errp, "failover primary device is not an "
+ "Ethernet device");
+ error_propagate(errp, local_err);
+ pci_qdev_unrealize(DEVICE(pci_dev), NULL);
+ return;
+ }
+ if (!(pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)
+ && (PCI_FUNC(pci_dev->devfn) == 0)) {
+ qdev->allow_unplug_during_migration = true;
+ } else {
+ error_setg(errp, "failover: primary device must be in its own "
+ "PCI slot");
+ error_propagate(errp, local_err);
+ pci_qdev_unrealize(DEVICE(pci_dev), NULL);
+ return;
+ }
+ qdev->allow_unplug_during_migration = true;
+ }
+
/* rom loading */
is_default_rom = false;
if (pci_dev->romfile == NULL && pc->romfile != NULL) {
{
PCIBus *bus = pci_get_bus(dev);
PCIBus *iommu_bus = bus;
+ uint8_t devfn = dev->devfn;
+
+ while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
+ PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev);
+
+ /*
+ * The requester ID of the provided device may be aliased, as seen from
+ * the IOMMU, due to topology limitations. The IOMMU relies on a
+ * requester ID to provide a unique AddressSpace for devices, but
+ * conventional PCI buses pre-date such concepts. Instead, the PCIe-
+ * to-PCI bridge creates and accepts transactions on behalf of down-
+ * stream devices. When doing so, all downstream devices are masked
+ * (aliased) behind a single requester ID. The requester ID used
+ * depends on the format of the bridge devices. Proper PCIe-to-PCI
+ * bridges, with a PCIe capability indicating such, follow the
+ * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification,
+ * where the bridge uses the seconary bus as the bridge portion of the
+ * requester ID and devfn of 00.0. For other bridges, typically those
+ * found on the root complex such as the dmi-to-pci-bridge, we follow
+ * the convention of typical bare-metal hardware, which uses the
+ * requester ID of the bridge itself. There are device specific
+ * exceptions to these rules, but these are the defaults that the
+ * Linux kernel uses when determining DMA aliases itself and believed
+ * to be true for the bare metal equivalents of the devices emulated
+ * in QEMU.
+ */
+ if (!pci_bus_is_express(iommu_bus)) {
+ PCIDevice *parent = iommu_bus->parent_dev;
+
+ if (pci_is_express(parent) &&
+ pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
+ devfn = PCI_DEVFN(0, 0);
+ bus = iommu_bus;
+ } else {
+ devfn = parent->devfn;
+ bus = parent_bus;
+ }
+ }
- while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
- iommu_bus = pci_get_bus(iommu_bus->parent_dev);
+ iommu_bus = parent_bus;
}
if (iommu_bus && iommu_bus->iommu_fn) {
- return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
+ return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn);
}
return &address_space_memory;
}
projects / mirror_qemu.git / blobdiff