hw/cxl/rp: Add a root port

[mirror_qemu.git] / hw / pci / pcie_port.c

diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c
index c19a9be59222970b0574f2485badaaf270f1a0df..e95c1e5519ce89f5b41682869ebe3c570b3bcd56 100644 (file)
--- a/hw/pci/pcie_port.c
+++ b/hw/pci/pcie_port.c
@@ -133,7 +133,7 @@ static void pcie_port_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
-    dc->props = pcie_port_props;
+    device_class_set_props(dc, pcie_port_props);
 }
 
 static const TypeInfo pcie_port_type_info = {
@@ -147,6 +147,8 @@ static const TypeInfo pcie_port_type_info = {
 static Property pcie_slot_props[] = {
     DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
     DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
+    DEFINE_PROP_BOOL("hotplug", PCIESlot, hotplug, true),
+    DEFINE_PROP_BOOL("x-native-hotplug", PCIESlot, native_hotplug, true),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -155,7 +157,7 @@ static void pcie_slot_class_init(ObjectClass *oc, void *data)
     DeviceClass *dc = DEVICE_CLASS(oc);
     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
 
-    dc->props = pcie_slot_props;
+    device_class_set_props(dc, pcie_slot_props);
     hc->pre_plug = pcie_cap_slot_pre_plug_cb;
     hc->plug = pcie_cap_slot_plug_cb;
     hc->unplug = pcie_cap_slot_unplug_cb;