-/*
- * Arm PrimeCell PL080 DMA controller
+/*
+ * Arm PrimeCell PL080/PL081 DMA controller
*
* Copyright (c) 2006 CodeSourcery.
* Written by Paul Brook
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "sysbus.h"
-#define PL080_NUM_CHANNELS 8
+#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E 0x1
#define PL080_CONF_M1 0x2
#define PL080_CONF_M2 0x4
} pl080_channel;
typedef struct {
- uint32_t base;
+ SysBusDevice busdev;
uint8_t tc_int;
uint8_t tc_mask;
uint8_t err_int;
uint32_t sync;
uint32_t req_single;
uint32_t req_burst;
- pl080_channel chan[PL080_NUM_CHANNELS];
+ pl080_channel chan[PL080_MAX_CHANNELS];
+ int nchannels;
/* Flag to avoid recursive DMA invocations. */
int running;
- void *pic;
- int irq;
+ qemu_irq irq;
} pl080_state;
static const unsigned char pl080_id[] =
{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
+static const unsigned char pl081_id[] =
+{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
+
static void pl080_update(pl080_state *s)
{
if ((s->tc_int & s->tc_mask)
|| (s->err_int & s->err_mask))
- pic_set_irq_new(s->pic, s->irq, 1);
+ qemu_irq_raise(s->irq);
else
- pic_set_irq_new(s->pic, s->irq, 1);
+ qemu_irq_lower(s->irq);
}
static void pl080_run(pl080_state *s)
int src_id;
int dest_id;
int size;
- char buff[4];
+ uint8_t buff[4];
uint32_t req;
s->tc_mask = 0;
- for (c = 0; c < PL080_NUM_CHANNELS; c++) {
+ for (c = 0; c < s->nchannels; c++) {
if (s->chan[c].conf & PL080_CCONF_ITC)
s->tc_mask |= 1 << c;
if (s->chan[c].conf & PL080_CCONF_IE)
if ((s->conf & PL080_CONF_E) == 0)
return;
-cpu_abort(cpu_single_env, "DMA active\n");
+hw_error("DMA active\n");
/* If we are already in the middle of a DMA operation then indicate that
there may be new DMA requests and return immediately. */
if (s->running) {
}
s->running = 1;
while (s->running) {
- for (c = 0; c < PL080_NUM_CHANNELS; c++) {
+ for (c = 0; c < s->nchannels; c++) {
ch = &s->chan[c];
again:
/* Test if thiws channel has any pending DMA requests. */
continue;
flow = (ch->conf >> 11) & 7;
if (flow >= 4) {
- cpu_abort(cpu_single_env,
+ hw_error(
"pl080_run: Peripheral flow control not implemented\n");
}
src_id = (ch->conf >> 1) & 0x1f;
uint32_t i;
uint32_t mask;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
- return pl080_id[(offset - 0xfe0) >> 2];
+ if (s->nchannels == 8) {
+ return pl080_id[(offset - 0xfe0) >> 2];
+ } else {
+ return pl081_id[(offset - 0xfe0) >> 2];
+ }
}
if (offset >= 0x100 && offset < 0x200) {
i = (offset & 0xe0) >> 5;
+ if (i >= s->nchannels)
+ goto bad_offset;
switch (offset >> 2) {
case 0: /* SrcAddr */
return s->chan[i].src;
return s->err_int;
case 7: /* EnbldChns */
mask = 0;
- for (i = 0; i < PL080_NUM_CHANNELS; i++) {
+ for (i = 0; i < s->nchannels; i++) {
if (s->chan[i].conf & PL080_CCONF_E)
mask |= 1 << i;
}
return s->sync;
default:
bad_offset:
- cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", offset);
+ hw_error("pl080_read: Bad offset %x\n", (int)offset);
return 0;
}
}
pl080_state *s = (pl080_state *)opaque;
int i;
- offset -= s->base;
if (offset >= 0x100 && offset < 0x200) {
i = (offset & 0xe0) >> 5;
+ if (i >= s->nchannels)
+ goto bad_offset;
switch (offset >> 2) {
case 0: /* SrcAddr */
s->chan[i].src = value;
case 10: /* SoftLBReq */
case 11: /* SoftLSReq */
/* ??? Implement these. */
- cpu_abort(cpu_single_env, "pl080_write: Soft DMA not implemented\n");
+ hw_error("pl080_write: Soft DMA not implemented\n");
break;
case 12: /* Configuration */
s->conf = value;
if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
- cpu_abort(cpu_single_env,
- "pl080_write: Big-endian DMA not implemented\n");
+ hw_error("pl080_write: Big-endian DMA not implemented\n");
}
pl080_run(s);
break;
s->sync = value;
break;
default:
- cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", offset);
+ bad_offset:
+ hw_error("pl080_write: Bad offset %x\n", (int)offset);
}
pl080_update(s);
}
-static CPUReadMemoryFunc *pl080_readfn[] = {
+static CPUReadMemoryFunc * const pl080_readfn[] = {
pl080_read,
pl080_read,
pl080_read
};
-static CPUWriteMemoryFunc *pl080_writefn[] = {
+static CPUWriteMemoryFunc * const pl080_writefn[] = {
pl080_write,
pl080_write,
pl080_write
};
-void *pl080_init(uint32_t base, void *pic, int irq)
+static int pl08x_init(SysBusDevice *dev, int nchannels)
{
int iomemtype;
- pl080_state *s;
+ pl080_state *s = FROM_SYSBUS(pl080_state, dev);
- s = (pl080_state *)qemu_mallocz(sizeof(pl080_state));
- iomemtype = cpu_register_io_memory(0, pl080_readfn,
+ iomemtype = cpu_register_io_memory(pl080_readfn,
pl080_writefn, s);
- cpu_register_physical_memory(base, 0x00000fff, iomemtype);
- s->base = base;
- s->pic = pic;
- s->irq = irq;
+ sysbus_init_mmio(dev, 0x1000, iomemtype);
+ sysbus_init_irq(dev, &s->irq);
+ s->nchannels = nchannels;
/* ??? Save/restore. */
- return s;
+ return 0;
+}
+
+static int pl080_init(SysBusDevice *dev)
+{
+ return pl08x_init(dev, 8);
+}
+
+static int pl081_init(SysBusDevice *dev)
+{
+ return pl08x_init(dev, 2);
+}
+
+/* The PL080 and PL081 are the same except for the number of channels
+ they implement (8 and 2 respectively). */
+static void pl080_register_devices(void)
+{
+ sysbus_register_dev("pl080", sizeof(pl080_state), pl080_init);
+ sysbus_register_dev("pl081", sizeof(pl080_state), pl081_init);
}
+device_init(pl080_register_devices)
projects / mirror_qemu.git / blobdiff