*/
#include "qemu/osdep.h"
+#include "qemu-common.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "e500.h"
#include "e500-ccsr.h"
#include "net/net.h"
#include "qemu/config-file.h"
-#include "hw/hw.h"
#include "hw/char/serial.h"
#include "hw/pci/pci.h"
#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
#include "kvm_ppc.h"
#include "sysemu/device_tree.h"
#include "hw/ppc/openpic.h"
#include "hw/ppc/openpic_kvm.h"
#include "hw/ppc/ppc.h"
+#include "hw/qdev-properties.h"
#include "hw/loader.h"
#include "elf.h"
#include "hw/sysbus.h"
#include "hw/platform-bus.h"
#include "hw/net/fsl_etsec/etsec.h"
#include "hw/i2c/i2c.h"
+#include "hw/irq.h"
#define EPAPR_MAGIC (0x45504150)
#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
bool dry_run)
{
MachineState *machine = MACHINE(pms);
+ unsigned int smp_cpus = machine->smp.cpus;
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
CPUPPCState *env = first_cpu->env_ptr;
int ret = -1;
cpu_physical_memory_write(addr, fdt, fdt_size);
}
ret = fdt_size;
+ g_free(fdt);
out:
g_free(pci_map);
SysBusDevice *s;
int i, j, k;
MachineState *machine = MACHINE(pms);
+ unsigned int smp_cpus = machine->smp.cpus;
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
- dev = qdev_create(NULL, TYPE_OPENPIC);
- object_property_add_child(OBJECT(machine), "pic", OBJECT(dev),
- &error_fatal);
+ dev = qdev_new(TYPE_OPENPIC);
+ object_property_add_child(OBJECT(machine), "pic", OBJECT(dev));
qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
k = 0;
for (i = 0; i < smp_cpus; i++) {
static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
IrqLines *irqs, Error **errp)
{
- Error *err = NULL;
DeviceState *dev;
CPUState *cs;
- dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
+ dev = qdev_new(TYPE_KVM_OPENPIC);
qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
- object_property_set_bool(OBJECT(dev), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
object_unparent(OBJECT(dev));
return NULL;
}
MemoryRegion *ccsr,
IrqLines *irqs)
{
- MachineState *machine = MACHINE(pms);
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
DeviceState *dev = NULL;
SysBusDevice *s;
if (kvm_enabled()) {
Error *err = NULL;
- if (machine_kernel_irqchip_allowed(machine)) {
+ if (kvm_kernel_irqchip_allowed()) {
dev = ppce500_init_mpic_kvm(pmc, irqs, &err);
}
- if (machine_kernel_irqchip_required(machine) && !dev) {
+ if (kvm_kernel_irqchip_required() && !dev) {
error_reportf_err(err,
"kernel_irqchip requested but unavailable: ");
exit(1);
void ppce500_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
- MemoryRegion *ram = g_new(MemoryRegion, 1);
PPCE500MachineState *pms = PPCE500_MACHINE(machine);
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
PCIBus *pci_bus;
struct boot_info *boot_info;
int dt_size;
int i;
+ unsigned int smp_cpus = machine->smp.cpus;
/* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
* 4 respectively */
unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
env = firstenv;
- /* Fixup Memory size on a alignment boundary */
- ram_size &= ~(RAM_SIZES_ALIGN - 1);
- machine->ram_size = ram_size;
+ if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) {
+ error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN);
+ exit(EXIT_FAILURE);
+ }
/* Register Memory */
- memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size);
- memory_region_add_subregion(address_space_mem, 0, ram);
+ memory_region_add_subregion(address_space_mem, 0, machine->ram);
- dev = qdev_create(NULL, "e500-ccsr");
+ dev = qdev_new("e500-ccsr");
object_property_add_child(qdev_get_machine(), "e500-ccsr",
- OBJECT(dev), NULL);
- qdev_init_nofail(dev);
+ OBJECT(dev));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ccsr = CCSR(dev);
ccsr_addr_space = &ccsr->ccsr_space;
memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
serial_hd(1), DEVICE_BIG_ENDIAN);
}
/* I2C */
- dev = qdev_create(NULL, "mpc-i2c");
+ dev = qdev_new("mpc-i2c");
s = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
sysbus_mmio_get_region(s, 0));
/* General Utility device */
- dev = qdev_create(NULL, "mpc8544-guts");
- qdev_init_nofail(dev);
+ dev = qdev_new("mpc8544-guts");
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
sysbus_mmio_get_region(s, 0));
/* PCI */
- dev = qdev_create(NULL, "e500-pcihost");
- object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev),
- &error_abort);
+ dev = qdev_new("e500-pcihost");
+ object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev));
qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
- qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
}
if (pmc->has_mpc8xxx_gpio) {
qemu_irq poweroff_irq;
- dev = qdev_create(NULL, "mpc8xxx_gpio");
+ dev = qdev_new("mpc8xxx_gpio");
s = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
sysbus_mmio_get_region(s, 0));
/* Platform Bus Device */
if (pmc->has_platform_bus) {
- dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
+ dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
dev->id = TYPE_PLATFORM_BUS_DEVICE;
qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
s = SYS_BUS_DEVICE(pms->pbus_dev);
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name);
+ if (!filename) {
+ error_report("could not find firmware/kernel file '%s'", payload_name);
+ exit(1);
+ }
payload_size = load_elf(filename, NULL, NULL, NULL,
- &bios_entry, &loadaddr, NULL,
+ &bios_entry, &loadaddr, NULL, NULL,
1, PPC_ELF_MACHINE, 0, 0);
if (payload_size < 0) {
/*
kernel_base = cur_base;
kernel_size = load_image_targphys(machine->kernel_filename,
cur_base,
- ram_size - cur_base);
+ machine->ram_size - cur_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'",
machine->kernel_filename);
if (machine->initrd_filename) {
initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
- ram_size - initrd_base);
+ machine->ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
* ensures enough space between kernel and initrd.
*/
dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
- if (dt_base + DTB_MAX_SIZE > ram_size) {
+ if (dt_base + DTB_MAX_SIZE > machine->ram_size) {
error_report("not enough memory for device tree");
exit(1);
}
projects / mirror_qemu.git / blobdiff