#include "sysemu/sysemu.h"
#include "qapi/error.h"
#include "qemu/log.h"
-#include "target-ppc/cpu.h"
+#include "target/ppc/cpu.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/xics.h"
-static void powernv_cpu_reset(void *opaque)
+static const char *pnv_core_cpu_typename(PnvCore *pc)
+{
+ const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
+ int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
+ char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
+ const char *cpu_type = object_class_get_name(object_class_by_name(s));
+ g_free(s);
+ return cpu_type;
+}
+
+static void pnv_cpu_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
CPUState *cs = CPU(cpu);
env->msr |= MSR_HVB; /* Hypervisor mode */
}
-static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
-{
- CPUPPCState *env = &cpu->env;
- int core_pir;
- int thread_index = 0; /* TODO: TCG supports only one thread */
- ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
-
- core_pir = object_property_get_int(OBJECT(cpu), "core-pir", &error_abort);
-
- /*
- * The PIR of a thread is the core PIR + the thread index. We will
- * need to find a way to get the thread index when TCG supports
- * more than 1. We could use the object name ?
- */
- pir->default_value = core_pir + thread_index;
-
- /* Set time-base frequency to 512 MHz */
- cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
-
- qemu_register_reset(powernv_cpu_reset, cpu);
-}
-
/*
* These values are read by the PowerNV HW monitors under Linux
*/
val = 0x24f000000000000ull;
break;
default:
- qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx,
+ qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
addr);
}
static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int width)
{
- qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx,
+ qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
addr);
}
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_core_realize_child(Object *child, Error **errp)
+static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabric *xi, Error **errp)
{
+ CPUPPCState *env = &cpu->env;
+ int core_pir;
+ int thread_index = 0; /* TODO: TCG supports only one thread */
+ ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
Error *local_err = NULL;
- CPUState *cs = CPU(child);
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- object_property_set_bool(child, true, "realized", &local_err);
+ object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- powernv_cpu_init(cpu, &local_err);
+ cpu->intc = icp_create(OBJECT(cpu), TYPE_PNV_ICP, xi, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
+
+ core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
+
+ /*
+ * The PIR of a thread is the core PIR + the thread index. We will
+ * need to find a way to get the thread index when TCG supports
+ * more than 1. We could use the object name ?
+ */
+ pir->default_value = core_pir + thread_index;
+
+ /* Set time-base frequency to 512 MHz */
+ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
+
+ qemu_register_reset(pnv_cpu_reset, cpu);
}
static void pnv_core_realize(DeviceState *dev, Error **errp)
{
PnvCore *pc = PNV_CORE(OBJECT(dev));
CPUCore *cc = CPU_CORE(OBJECT(dev));
- PnvCoreClass *pcc = PNV_CORE_GET_CLASS(OBJECT(dev));
- const char *typename = object_class_get_name(pcc->cpu_oc);
- size_t size = object_type_get_instance_size(typename);
+ const char *typename = pnv_core_cpu_typename(pc);
Error *local_err = NULL;
void *obj;
int i, j;
char name[32];
+ Object *xi;
+
+ xi = object_property_get_link(OBJECT(dev), "xics", &local_err);
+ if (!xi) {
+ error_setg(errp, "%s: required link 'xics' not found: %s",
+ __func__, error_get_pretty(local_err));
+ return;
+ }
- pc->threads = g_malloc0(size * cc->nr_threads);
+ pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
- obj = pc->threads + i * size;
+ obj = object_new(typename);
- object_initialize(obj, size, typename);
+ pc->threads[i] = POWERPC_CPU(obj);
snprintf(name, sizeof(name), "thread[%d]", i);
- object_property_add_child(OBJECT(pc), name, obj, &local_err);
+ object_property_add_child(OBJECT(pc), name, obj, &error_abort);
object_property_add_alias(obj, "core-pir", OBJECT(pc),
- "pir", &local_err);
- if (local_err) {
- goto err;
- }
+ "pir", &error_abort);
object_unref(obj);
}
for (j = 0; j < cc->nr_threads; j++) {
- obj = pc->threads + j * size;
-
- pnv_core_realize_child(obj, &local_err);
+ pnv_realize_vcpu(pc->threads[j], XICS_FABRIC(xi), &local_err);
if (local_err) {
goto err;
}
snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops,
- pc, name, PNV_XSCOM_EX_CORE_SIZE);
+ pc, name, PNV_XSCOM_EX_SIZE);
return;
err:
while (--i >= 0) {
- obj = pc->threads + i * size;
+ obj = OBJECT(pc->threads[i]);
object_unparent(obj);
}
g_free(pc->threads);
error_propagate(errp, local_err);
}
+static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
+{
+ qemu_unregister_reset(pnv_cpu_reset, cpu);
+ object_unparent(cpu->intc);
+ cpu_remove_sync(CPU(cpu));
+ object_unparent(OBJECT(cpu));
+}
+
+static void pnv_core_unrealize(DeviceState *dev, Error **errp)
+{
+ PnvCore *pc = PNV_CORE(dev);
+ CPUCore *cc = CPU_CORE(dev);
+ int i;
+
+ for (i = 0; i < cc->nr_threads; i++) {
+ pnv_unrealize_vcpu(pc->threads[i]);
+ }
+ g_free(pc->threads);
+}
+
static Property pnv_core_properties[] = {
DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
DEFINE_PROP_END_OF_LIST(),
static void pnv_core_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
dc->realize = pnv_core_realize;
+ dc->unrealize = pnv_core_unrealize;
dc->props = pnv_core_properties;
- pcc->cpu_oc = cpu_class_by_name(TYPE_POWERPC_CPU, data);
}
-static const TypeInfo pnv_core_info = {
- .name = TYPE_PNV_CORE,
- .parent = TYPE_CPU_CORE,
- .instance_size = sizeof(PnvCore),
- .class_size = sizeof(PnvCoreClass),
- .abstract = true,
-};
-
-static const char *pnv_core_models[] = {
- "POWER8E", "POWER8", "POWER8NVL", "POWER9"
-};
-
-static void pnv_core_register_types(void)
-{
- int i ;
-
- type_register_static(&pnv_core_info);
- for (i = 0; i < ARRAY_SIZE(pnv_core_models); ++i) {
- TypeInfo ti = {
- .parent = TYPE_PNV_CORE,
- .instance_size = sizeof(PnvCore),
- .class_init = pnv_core_class_init,
- .class_data = (void *) pnv_core_models[i],
- };
- ti.name = pnv_core_typename(pnv_core_models[i]);
- type_register(&ti);
- g_free((void *)ti.name);
+#define DEFINE_PNV_CORE_TYPE(cpu_model) \
+ { \
+ .parent = TYPE_PNV_CORE, \
+ .name = PNV_CORE_TYPE_NAME(cpu_model), \
}
-}
-type_init(pnv_core_register_types)
+static const TypeInfo pnv_core_infos[] = {
+ {
+ .name = TYPE_PNV_CORE,
+ .parent = TYPE_CPU_CORE,
+ .instance_size = sizeof(PnvCore),
+ .class_size = sizeof(PnvCoreClass),
+ .class_init = pnv_core_class_init,
+ .abstract = true,
+ },
+ DEFINE_PNV_CORE_TYPE("power8e_v2.1"),
+ DEFINE_PNV_CORE_TYPE("power8_v2.0"),
+ DEFINE_PNV_CORE_TYPE("power8nvl_v1.0"),
+ DEFINE_PNV_CORE_TYPE("power9_v2.0"),
+};
-char *pnv_core_typename(const char *model)
-{
- return g_strdup_printf(TYPE_PNV_CORE "-%s", model);
-}
+DEFINE_TYPES(pnv_core_infos)
projects / mirror_qemu.git / blobdiff