uint32_t besr;
};
-static target_ulong dcr_read_plb (void *opaque, int dcrn)
+static uint32_t dcr_read_plb (void *opaque, int dcrn)
{
ppc4xx_plb_t *plb;
- target_ulong ret;
+ uint32_t ret;
plb = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
{
ppc4xx_plb_t *plb;
plb->besr = 0x00000000;
}
-void ppc4xx_plb_init (CPUState *env)
+static void ppc4xx_plb_init(CPUState *env)
{
ppc4xx_plb_t *plb;
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc4xx_plb_reset(plb);
- qemu_register_reset(ppc4xx_plb_reset, 0, plb);
+ qemu_register_reset(ppc4xx_plb_reset, plb);
}
/*****************************************************************************/
uint32_t besr[2];
};
-static target_ulong dcr_read_pob (void *opaque, int dcrn)
+static uint32_t dcr_read_pob (void *opaque, int dcrn)
{
ppc4xx_pob_t *pob;
- target_ulong ret;
+ uint32_t ret;
pob = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
{
ppc4xx_pob_t *pob;
pob->besr[1] = 0x0000000;
}
-void ppc4xx_pob_init (CPUState *env)
+static void ppc4xx_pob_init(CPUState *env)
{
ppc4xx_pob_t *pob;
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
- qemu_register_reset(ppc4xx_pob_reset, 0, pob);
- ppc4xx_pob_reset(env);
+ qemu_register_reset(ppc4xx_pob_reset, pob);
}
/*****************************************************************************/
/* OPB arbitrer */
typedef struct ppc4xx_opba_t ppc4xx_opba_t;
struct ppc4xx_opba_t {
- target_phys_addr_t base;
uint8_t cr;
uint8_t pr;
};
uint32_t ret;
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
opba = opaque;
- switch (addr - opba->base) {
+ switch (addr) {
case 0x00:
ret = opba->cr;
break;
ppc4xx_opba_t *opba;
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
opba = opaque;
- switch (addr - opba->base) {
+ switch (addr) {
case 0x00:
opba->cr = value & 0xF8;
break;
uint32_t ret;
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = opba_readb(opaque, addr) << 8;
ret |= opba_readb(opaque, addr + 1);
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
opba_writeb(opaque, addr, value >> 8);
opba_writeb(opaque, addr + 1, value);
uint32_t ret;
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = opba_readb(opaque, addr) << 24;
ret |= opba_readb(opaque, addr + 1) << 16;
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
opba_writeb(opaque, addr, value >> 24);
opba_writeb(opaque, addr + 1, value >> 16);
}
-static CPUReadMemoryFunc *opba_read[] = {
+static CPUReadMemoryFunc * const opba_read[] = {
&opba_readb,
&opba_readw,
&opba_readl,
};
-static CPUWriteMemoryFunc *opba_write[] = {
+static CPUWriteMemoryFunc * const opba_write[] = {
&opba_writeb,
&opba_writew,
&opba_writel,
opba->pr = 0x11;
}
-void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
- target_phys_addr_t offset)
+static void ppc4xx_opba_init(target_phys_addr_t base)
{
ppc4xx_opba_t *opba;
+ int io;
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
- opba->base = offset;
#ifdef DEBUG_OPBA
- printf("%s: offset " PADDRX "\n", __func__, offset);
+ printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- ppc4xx_mmio_register(env, mmio, offset, 0x002,
- opba_read, opba_write, opba);
- qemu_register_reset(ppc4xx_opba_reset, 0, opba);
- ppc4xx_opba_reset(opba);
+ io = cpu_register_io_memory(opba_read, opba_write, opba,
+ DEVICE_NATIVE_ENDIAN);
+ cpu_register_physical_memory(base, 0x002, io);
+ qemu_register_reset(ppc4xx_opba_reset, opba);
}
/*****************************************************************************/
EBC0_CFGDATA = 0x013,
};
-static target_ulong dcr_read_ebc (void *opaque, int dcrn)
+static uint32_t dcr_read_ebc (void *opaque, int dcrn)
{
ppc4xx_ebc_t *ebc;
- target_ulong ret;
+ uint32_t ret;
ebc = opaque;
switch (dcrn) {
ret = 0x00000000;
break;
}
+ break;
default:
ret = 0x00000000;
break;
return ret;
}
-static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
{
ppc4xx_ebc_t *ebc;
ebc->cfg = 0x80400000;
}
-void ppc405_ebc_init (CPUState *env)
+static void ppc405_ebc_init(CPUState *env)
{
ppc4xx_ebc_t *ebc;
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
- ebc_reset(ebc);
- qemu_register_reset(&ebc_reset, 0, ebc);
+ qemu_register_reset(&ebc_reset, ebc);
ppc_dcr_register(env, EBC0_CFGADDR,
ebc, &dcr_read_ebc, &dcr_write_ebc);
ppc_dcr_register(env, EBC0_CFGDATA,
uint32_t pol;
};
-static target_ulong dcr_read_dma (void *opaque, int dcrn)
+static uint32_t dcr_read_dma (void *opaque, int dcrn)
{
- ppc405_dma_t *dma;
-
- dma = opaque;
-
return 0;
}
-static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
{
- ppc405_dma_t *dma;
-
- dma = opaque;
}
static void ppc405_dma_reset (void *opaque)
dma->pol = 0x00000000;
}
-void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
+static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
{
ppc405_dma_t *dma;
dma = qemu_mallocz(sizeof(ppc405_dma_t));
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
- ppc405_dma_reset(dma);
- qemu_register_reset(&ppc405_dma_reset, 0, dma);
+ qemu_register_reset(&ppc405_dma_reset, dma);
ppc_dcr_register(env, DMA0_CR0,
dma, &dcr_read_dma, &dcr_write_dma);
ppc_dcr_register(env, DMA0_CT0,
/* GPIO */
typedef struct ppc405_gpio_t ppc405_gpio_t;
struct ppc405_gpio_t {
- target_phys_addr_t base;
uint32_t or;
uint32_t tcr;
uint32_t osrh;
static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
static void ppc405_gpio_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
}
static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
static void ppc405_gpio_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
}
static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
static void ppc405_gpio_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
}
-static CPUReadMemoryFunc *ppc405_gpio_read[] = {
+static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
&ppc405_gpio_readb,
&ppc405_gpio_readw,
&ppc405_gpio_readl,
};
-static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
+static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
&ppc405_gpio_writeb,
&ppc405_gpio_writew,
&ppc405_gpio_writel,
static void ppc405_gpio_reset (void *opaque)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
}
-void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
- target_phys_addr_t offset)
+static void ppc405_gpio_init(target_phys_addr_t base)
{
ppc405_gpio_t *gpio;
+ int io;
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
- gpio->base = offset;
- ppc405_gpio_reset(gpio);
- qemu_register_reset(&ppc405_gpio_reset, 0, gpio);
#ifdef DEBUG_GPIO
- printf("%s: offset " PADDRX "\n", __func__, offset);
-#endif
- ppc4xx_mmio_register(env, mmio, offset, 0x038,
- ppc405_gpio_read, ppc405_gpio_write, gpio);
-}
-
-/*****************************************************************************/
-/* Serial ports */
-static CPUReadMemoryFunc *serial_mm_read[] = {
- &serial_mm_readb,
- &serial_mm_readw,
- &serial_mm_readl,
-};
-
-static CPUWriteMemoryFunc *serial_mm_write[] = {
- &serial_mm_writeb,
- &serial_mm_writew,
- &serial_mm_writel,
-};
-
-void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
- target_phys_addr_t offset, qemu_irq irq,
- CharDriverState *chr)
-{
- void *serial;
-
-#ifdef DEBUG_SERIAL
- printf("%s: offset " PADDRX "\n", __func__, offset);
+ printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- serial = serial_mm_init(offset, 0, irq, 399193, chr, 0);
- ppc4xx_mmio_register(env, mmio, offset, 0x008,
- serial_mm_read, serial_mm_write, serial);
+ io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
+ DEVICE_NATIVE_ENDIAN);
+ cpu_register_physical_memory(base, 0x038, io);
+ qemu_register_reset(&ppc405_gpio_reset, gpio);
}
/*****************************************************************************/
}
}
-static target_ulong dcr_read_ocm (void *opaque, int dcrn)
+static uint32_t dcr_read_ocm (void *opaque, int dcrn)
{
ppc405_ocm_t *ocm;
- target_ulong ret;
+ uint32_t ret;
ocm = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
{
ppc405_ocm_t *ocm;
uint32_t isarc, dsarc, isacntl, dsacntl;
ocm->dsacntl = dsacntl;
}
-void ppc405_ocm_init (CPUState *env)
+static void ppc405_ocm_init(CPUState *env)
{
ppc405_ocm_t *ocm;
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
- ocm->offset = qemu_ram_alloc(4096);
- ocm_reset(ocm);
- qemu_register_reset(&ocm_reset, 0, ocm);
+ ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096);
+ qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
ppc_dcr_register(env, OCM0_ISACNTL,
/* I2C controller */
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
struct ppc4xx_i2c_t {
- target_phys_addr_t base;
qemu_irq irq;
uint8_t mdata;
uint8_t lmadr;
uint32_t ret;
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
i2c = opaque;
- switch (addr - i2c->base) {
+ switch (addr) {
case 0x00:
// i2c_readbyte(&i2c->mdata);
ret = i2c->mdata;
break;
}
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
+ printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
#endif
return ret;
ppc4xx_i2c_t *i2c;
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
i2c = opaque;
- switch (addr - i2c->base) {
+ switch (addr) {
case 0x00:
i2c->mdata = value;
// i2c_sendbyte(&i2c->mdata);
uint32_t ret;
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = ppc4xx_i2c_readb(opaque, addr) << 8;
ret |= ppc4xx_i2c_readb(opaque, addr + 1);
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
ppc4xx_i2c_writeb(opaque, addr, value >> 8);
ppc4xx_i2c_writeb(opaque, addr + 1, value);
uint32_t ret;
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = ppc4xx_i2c_readb(opaque, addr) << 24;
ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
ppc4xx_i2c_writeb(opaque, addr, value >> 24);
ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
ppc4xx_i2c_writeb(opaque, addr + 3, value);
}
-static CPUReadMemoryFunc *i2c_read[] = {
+static CPUReadMemoryFunc * const i2c_read[] = {
&ppc4xx_i2c_readb,
&ppc4xx_i2c_readw,
&ppc4xx_i2c_readl,
};
-static CPUWriteMemoryFunc *i2c_write[] = {
+static CPUWriteMemoryFunc * const i2c_write[] = {
&ppc4xx_i2c_writeb,
&ppc4xx_i2c_writew,
&ppc4xx_i2c_writel,
i2c->directcntl = 0x0F;
}
-void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
- target_phys_addr_t offset, qemu_irq irq)
+static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
{
ppc4xx_i2c_t *i2c;
+ int io;
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
- i2c->base = offset;
i2c->irq = irq;
- ppc4xx_i2c_reset(i2c);
#ifdef DEBUG_I2C
- printf("%s: offset " PADDRX "\n", __func__, offset);
+ printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- ppc4xx_mmio_register(env, mmio, offset, 0x011,
- i2c_read, i2c_write, i2c);
- qemu_register_reset(ppc4xx_i2c_reset, 0, i2c);
+ io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
+ DEVICE_NATIVE_ENDIAN);
+ cpu_register_physical_memory(base, 0x011, io);
+ qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
/*****************************************************************************/
/* General purpose timers */
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
struct ppc4xx_gpt_t {
- target_phys_addr_t base;
int64_t tb_offset;
uint32_t tb_freq;
struct QEMUTimer *timer;
static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_GPT
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
/* XXX: generate a bus fault */
return -1;
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
/* XXX: generate a bus fault */
}
static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_GPT
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
/* XXX: generate a bus fault */
return -1;
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
/* XXX: generate a bus fault */
}
int idx;
#ifdef DEBUG_GPT
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
gpt = opaque;
- switch (addr - gpt->base) {
+ switch (addr) {
case 0x00:
/* Time base counter */
ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
- gpt->tb_freq, ticks_per_sec);
+ gpt->tb_freq, get_ticks_per_sec());
break;
case 0x10:
/* Output enable */
break;
case 0x80 ... 0x90:
/* Compare timer */
- idx = ((addr - gpt->base) - 0x80) >> 2;
+ idx = (addr - 0x80) >> 2;
ret = gpt->comp[idx];
break;
case 0xC0 ... 0xD0:
/* Compare mask */
- idx = ((addr - gpt->base) - 0xC0) >> 2;
+ idx = (addr - 0xC0) >> 2;
ret = gpt->mask[idx];
break;
default:
int idx;
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
gpt = opaque;
- switch (addr - gpt->base) {
+ switch (addr) {
case 0x00:
/* Time base counter */
- gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
+ gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
- qemu_get_clock(vm_clock);
ppc4xx_gpt_compute_timer(gpt);
break;
break;
case 0x80 ... 0x90:
/* Compare timer */
- idx = ((addr - gpt->base) - 0x80) >> 2;
+ idx = (addr - 0x80) >> 2;
gpt->comp[idx] = value & 0xF8000000;
ppc4xx_gpt_compute_timer(gpt);
break;
case 0xC0 ... 0xD0:
/* Compare mask */
- idx = ((addr - gpt->base) - 0xC0) >> 2;
+ idx = (addr - 0xC0) >> 2;
gpt->mask[idx] = value & 0xF8000000;
ppc4xx_gpt_compute_timer(gpt);
break;
}
}
-static CPUReadMemoryFunc *gpt_read[] = {
+static CPUReadMemoryFunc * const gpt_read[] = {
&ppc4xx_gpt_readb,
&ppc4xx_gpt_readw,
&ppc4xx_gpt_readl,
};
-static CPUWriteMemoryFunc *gpt_write[] = {
+static CPUWriteMemoryFunc * const gpt_write[] = {
&ppc4xx_gpt_writeb,
&ppc4xx_gpt_writew,
&ppc4xx_gpt_writel,
}
}
-void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
- target_phys_addr_t offset, qemu_irq irqs[5])
+static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
{
ppc4xx_gpt_t *gpt;
int i;
+ int io;
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
- gpt->base = offset;
- for (i = 0; i < 5; i++)
+ for (i = 0; i < 5; i++) {
gpt->irqs[i] = irqs[i];
+ }
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
- ppc4xx_gpt_reset(gpt);
#ifdef DEBUG_GPT
- printf("%s: offset " PADDRX "\n", __func__, offset);
+ printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
- gpt_read, gpt_write, gpt);
- qemu_register_reset(ppc4xx_gpt_reset, 0, gpt);
+ io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
+ cpu_register_physical_memory(base, 0x0d4, io);
+ qemu_register_reset(ppc4xx_gpt_reset, gpt);
}
/*****************************************************************************/
static void ppc40x_mal_reset (void *opaque);
-static target_ulong dcr_read_mal (void *opaque, int dcrn)
+static uint32_t dcr_read_mal (void *opaque, int dcrn)
{
ppc40x_mal_t *mal;
- target_ulong ret;
+ uint32_t ret;
mal = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
{
ppc40x_mal_t *mal;
int idx;
mal->txeobisr = 0x00000000;
}
-void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
+static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
{
ppc40x_mal_t *mal;
int i;
mal = qemu_mallocz(sizeof(ppc40x_mal_t));
for (i = 0; i < 4; i++)
mal->irqs[i] = irqs[i];
- ppc40x_mal_reset(mal);
- qemu_register_reset(&ppc40x_mal_reset, 0, mal);
+ qemu_register_reset(&ppc40x_mal_reset, mal);
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_ESR,
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
- cpu_ppc_reset(env);
+ cpu_reset(env);
#else
qemu_system_reset_request();
#endif
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
- cpu_ppc_reset(env);
+ cpu_reset(env);
#else
qemu_system_reset_request();
#endif
clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
}
-static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
+static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
{
ppc405cr_cpc_t *cpc;
- target_ulong ret;
+ uint32_t ret;
cpc = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
{
ppc405cr_cpc_t *cpc;
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc405cr_clk_init(cpc);
- qemu_register_reset(ppc405cr_cpc_reset, 0, cpc);
- ppc405cr_cpc_reset(cpc);
+ qemu_register_reset(ppc405cr_cpc_reset, cpc);
}
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
clk_setup_t clk_setup[PPC405CR_CLK_NB];
qemu_irq dma_irqs[4];
CPUState *env;
- ppc4xx_mmio_t *mmio;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
&clk_setup[PPC405CR_TMR_CLK], sysclk);
/* Memory mapped devices registers */
- mmio = ppc4xx_mmio_init(env, 0xEF600000);
/* PLB arbitrer */
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
ppc4xx_pob_init(env);
/* OBP arbitrer */
- ppc4xx_opba_init(env, mmio, 0x600);
+ ppc4xx_opba_init(0xef600600);
/* Universal interrupt controller */
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] =
ppc405_dma_init(env, dma_irqs);
/* Serial ports */
if (serial_hds[0] != NULL) {
- ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
+ serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
+ serial_hds[0], 1, 1);
}
if (serial_hds[1] != NULL) {
- ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
+ serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
+ serial_hds[1], 1, 1);
}
/* IIC controller */
- ppc405_i2c_init(env, mmio, 0x500, pic[2]);
+ ppc405_i2c_init(0xef600500, pic[2]);
/* GPIO */
- ppc405_gpio_init(env, mmio, 0x700);
+ ppc405_gpio_init(0xef600700);
/* CPU control */
ppc405cr_cpc_init(env, clk_setup, sysclk);
clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
}
-static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
+static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
{
ppc405ep_cpc_t *cpc;
- target_ulong ret;
+ uint32_t ret;
cpc = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
{
ppc405ep_cpc_t *cpc;
PPC405EP_CLK_NB * sizeof(clk_setup_t));
cpc->jtagid = 0x20267049;
cpc->sysclk = sysclk;
- ppc405ep_cpc_reset(cpc);
- qemu_register_reset(&ppc405ep_cpc_reset, 0, cpc);
+ qemu_register_reset(&ppc405ep_cpc_reset, cpc);
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUState *env;
- ppc4xx_mmio_t *mmio;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
/* Internal devices init */
/* Memory mapped devices registers */
- mmio = ppc4xx_mmio_init(env, 0xEF600000);
/* PLB arbitrer */
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
ppc4xx_pob_init(env);
/* OBP arbitrer */
- ppc4xx_opba_init(env, mmio, 0x600);
+ ppc4xx_opba_init(0xef600600);
/* Universal interrupt controller */
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] =
dma_irqs[3] = pic[8];
ppc405_dma_init(env, dma_irqs);
/* IIC controller */
- ppc405_i2c_init(env, mmio, 0x500, pic[2]);
+ ppc405_i2c_init(0xef600500, pic[2]);
/* GPIO */
- ppc405_gpio_init(env, mmio, 0x700);
+ ppc405_gpio_init(0xef600700);
/* Serial ports */
if (serial_hds[0] != NULL) {
- ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
+ serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
+ serial_hds[0], 1, 1);
}
if (serial_hds[1] != NULL) {
- ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
+ serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
+ serial_hds[1], 1, 1);
}
/* OCM */
ppc405_ocm_init(env);
gpt_irqs[2] = pic[21];
gpt_irqs[3] = pic[22];
gpt_irqs[4] = pic[23];
- ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
+ ppc4xx_gpt_init(0xef600000, gpt_irqs);
/* PCI */
/* Uses pic[3], pic[16], pic[18] */
/* MAL */
projects / mirror_qemu.git / blobdiff