#include "hw.h"
#include "ppc.h"
#include "ppc4xx.h"
-#include "sysemu.h"
#include "qemu-log.h"
+#include "exec/address-spaces.h"
//#define DEBUG_MMIO
//#define DEBUG_UNASSIGNED
# define LOG_UIC(...) do { } while (0)
#endif
+static void ppc4xx_reset(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+
+ cpu_reset(CPU(cpu));
+}
+
/*****************************************************************************/
-/* Generic PowerPC 4xx processor instanciation */
-CPUState *ppc4xx_init (const char *cpu_model,
- a_clk_setup *cpu_clk, a_clk_setup *tb_clk,
+/* Generic PowerPC 4xx processor instantiation */
+CPUPPCState *ppc4xx_init (const char *cpu_model,
+ clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk)
{
- CPUState *env;
+ PowerPCCPU *cpu;
+ CPUPPCState *env;
/* init CPUs */
- env = cpu_init(cpu_model);
- if (!env) {
+ cpu = cpu_ppc_init(cpu_model);
+ if (cpu == NULL) {
fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
cpu_model);
exit(1);
}
+ env = &cpu->env;
+
cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
cpu_clk->opaque = env;
/* Set time-base frequency to sysclk */
- tb_clk->cb = ppc_emb_timers_init(env, sysclk);
+ tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT);
tb_clk->opaque = env;
ppc_dcr_init(env, NULL, NULL);
/* Register qemu callbacks */
- qemu_register_reset(&cpu_ppc_reset, env);
+ qemu_register_reset(ppc4xx_reset, cpu);
return env;
}
};
#define UIC_MAX_IRQ 32
-typedef struct ppcuic a_ppcuic;
-struct ppcuic {
+typedef struct ppcuic_t ppcuic_t;
+struct ppcuic_t {
uint32_t dcr_base;
int use_vectors;
uint32_t level; /* Remembers the state of level-triggered interrupts. */
qemu_irq *irqs;
};
-static void ppcuic_trigger_irq (a_ppcuic *uic)
+static void ppcuic_trigger_irq (ppcuic_t *uic)
{
uint32_t ir, cr;
int start, end, inc, i;
static void ppcuic_set_irq (void *opaque, int irq_num, int level)
{
- a_ppcuic *uic;
+ ppcuic_t *uic;
uint32_t mask, sr;
uic = opaque;
ppcuic_trigger_irq(uic);
}
-static target_ulong dcr_read_uic (void *opaque, int dcrn)
+static uint32_t dcr_read_uic (void *opaque, int dcrn)
{
- a_ppcuic *uic;
- target_ulong ret;
+ ppcuic_t *uic;
+ uint32_t ret;
uic = opaque;
dcrn -= uic->dcr_base;
return ret;
}
-static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
{
- a_ppcuic *uic;
+ ppcuic_t *uic;
uic = opaque;
dcrn -= uic->dcr_base;
- LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val);
+ LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;
static void ppcuic_reset (void *opaque)
{
- a_ppcuic *uic;
+ ppcuic_t *uic;
uic = opaque;
uic->uiccr = 0x00000000;
}
}
-qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
+qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr)
{
- a_ppcuic *uic;
+ ppcuic_t *uic;
int i;
- uic = qemu_mallocz(sizeof(a_ppcuic));
+ uic = g_malloc0(sizeof(ppcuic_t));
uic->dcr_base = dcr_base;
uic->irqs = irqs;
if (has_vr)
&dcr_read_uic, &dcr_write_uic);
}
qemu_register_reset(ppcuic_reset, uic);
- ppcuic_reset(uic);
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
}
/*****************************************************************************/
/* SDRAM controller */
-typedef struct ppc4xx_sdram a_ppc4xx_sdram;
-struct ppc4xx_sdram {
+typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
+struct ppc4xx_sdram_t {
uint32_t addr;
int nbanks;
- a_target_phys_addr ram_bases[4];
- a_target_phys_addr ram_sizes[4];
+ MemoryRegion containers[4]; /* used for clipping */
+ MemoryRegion *ram_memories;
+ hwaddr ram_bases[4];
+ hwaddr ram_sizes[4];
uint32_t besr0;
uint32_t besr1;
uint32_t bear;
};
/* XXX: TOFIX: some patches have made this code become inconsistent:
- * there are type inconsistencies, mixing a_target_phys_addr, target_ulong
+ * there are type inconsistencies, mixing hwaddr, target_ulong
* and uint32_t
*/
-static uint32_t sdram_bcr (a_target_phys_addr ram_base,
- a_target_phys_addr ram_size)
+static uint32_t sdram_bcr (hwaddr ram_base,
+ hwaddr ram_size)
{
uint32_t bcr;
return bcr;
}
-static inline a_target_phys_addr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
return size;
}
-static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
+static void sdram_set_bcr(ppc4xx_sdram_t *sdram,
+ uint32_t *bcrp, uint32_t bcr, int enabled)
{
+ unsigned n = bcrp - sdram->bcr;
+
if (*bcrp & 0x00000001) {
/* Unmap RAM */
#ifdef DEBUG_SDRAM
printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(*bcrp), sdram_size(*bcrp));
#endif
- cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->containers[n]);
+ memory_region_del_subregion(&sdram->containers[n],
+ &sdram->ram_memories[n]);
+ memory_region_destroy(&sdram->containers[n]);
}
*bcrp = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(bcr), sdram_size(bcr));
#endif
- cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
- sdram_base(bcr) | IO_MEM_RAM);
+ memory_region_init(&sdram->containers[n], "sdram-containers",
+ sdram_size(bcr));
+ memory_region_add_subregion(&sdram->containers[n], 0,
+ &sdram->ram_memories[n]);
+ memory_region_add_subregion(get_system_memory(),
+ sdram_base(bcr),
+ &sdram->containers[n]);
}
}
-static void sdram_map_bcr (a_ppc4xx_sdram *sdram)
+static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->ram_sizes[i] != 0) {
- sdram_set_bcr(&sdram->bcr[i],
+ sdram_set_bcr(sdram,
+ &sdram->bcr[i],
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
1);
} else {
- sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
+ sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0);
}
}
}
-static void sdram_unmap_bcr (a_ppc4xx_sdram *sdram)
+static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
{
int i;
printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
#endif
- cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
- sdram_size(sdram->bcr[i]),
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->ram_memories[i]);
}
}
-static target_ulong dcr_read_sdram (void *opaque, int dcrn)
+static uint32_t dcr_read_sdram (void *opaque, int dcrn)
{
- a_ppc4xx_sdram *sdram;
- target_ulong ret;
+ ppc4xx_sdram_t *sdram;
+ uint32_t ret;
sdram = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
{
- a_ppc4xx_sdram *sdram;
+ ppc4xx_sdram_t *sdram;
sdram = opaque;
switch (dcrn) {
sdram->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
- sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
- sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
- sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
sdram->tr = val & 0x018FC01F;
static void sdram_reset (void *opaque)
{
- a_ppc4xx_sdram *sdram;
+ ppc4xx_sdram_t *sdram;
sdram = opaque;
sdram->addr = 0x00000000;
/* We pre-initialize RAM banks */
sdram->status = 0x00000000;
sdram->cfg = 0x00800000;
- sdram_unmap_bcr(sdram);
}
-void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
- a_target_phys_addr *ram_bases,
- a_target_phys_addr *ram_sizes,
+void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
+ MemoryRegion *ram_memories,
+ hwaddr *ram_bases,
+ hwaddr *ram_sizes,
int do_init)
{
- a_ppc4xx_sdram *sdram;
+ ppc4xx_sdram_t *sdram;
- sdram = qemu_mallocz(sizeof(a_ppc4xx_sdram));
+ sdram = g_malloc0(sizeof(ppc4xx_sdram_t));
sdram->irq = irq;
sdram->nbanks = nbanks;
- memset(sdram->ram_bases, 0, 4 * sizeof(a_target_phys_addr));
+ sdram->ram_memories = ram_memories;
+ memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
memcpy(sdram->ram_bases, ram_bases,
- nbanks * sizeof(a_target_phys_addr));
- memset(sdram->ram_sizes, 0, 4 * sizeof(a_target_phys_addr));
+ nbanks * sizeof(hwaddr));
+ memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
memcpy(sdram->ram_sizes, ram_sizes,
- nbanks * sizeof(a_target_phys_addr));
- sdram_reset(sdram);
+ nbanks * sizeof(hwaddr));
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
* The 4xx SDRAM controller supports a small number of banks, and each bank
* must be one of a small set of sizes. The number of banks and the supported
* sizes varies by SoC. */
-a_ram_addr ppc4xx_sdram_adjust(a_ram_addr ram_size, int nr_banks,
- a_target_phys_addr ram_bases[],
- a_target_phys_addr ram_sizes[],
+ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ MemoryRegion ram_memories[],
+ hwaddr ram_bases[],
+ hwaddr ram_sizes[],
const unsigned int sdram_bank_sizes[])
{
- a_ram_addr size_left = ram_size;
+ ram_addr_t size_left = ram_size;
+ ram_addr_t base = 0;
int i;
int j;
unsigned int bank_size = sdram_bank_sizes[j];
if (bank_size <= size_left) {
- ram_bases[i] = qemu_ram_alloc(bank_size);
+ char name[32];
+ snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
+ memory_region_init_ram(&ram_memories[i], name, bank_size);
+ vmstate_register_ram_global(&ram_memories[i]);
+ ram_bases[i] = base;
ram_sizes[i] = bank_size;
+ base += ram_size;
size_left -= bank_size;
break;
}
}
ram_size -= size_left;
- if (ram_size)
+ if (size_left)
printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
(int)(ram_size >> 20));
projects / mirror_qemu.git / blobdiff