#include "hw.h"
#include "ppc.h"
#include "ppc4xx.h"
-
-typedef target_phys_addr_t pci_addr_t;
-#include "pci.h"
-#include "pci_host.h"
-#include "bswap.h"
+#include "pci/pci.h"
+#include "pci/pci_host.h"
+#include "exec/address-spaces.h"
#undef DEBUG
#ifdef DEBUG
uint32_t la;
};
+#define PPC4xx_PCI_HOST_BRIDGE(obj) \
+ OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)
+
#define PPC4xx_PCI_NR_PMMS 3
#define PPC4xx_PCI_NR_PTMS 2
struct PPC4xxPCIState {
+ PCIHostState parent_obj;
+
struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
+ qemu_irq irq[4];
- PCIHostState pci_state;
- PCIDevice *pci_dev;
+ MemoryRegion container;
+ MemoryRegion iomem;
};
typedef struct PPC4xxPCIState PPC4xxPCIState;
#define PCIL0_PTM1LA 0x34
#define PCIL0_PTM2MS 0x38
#define PCIL0_PTM2LA 0x3c
+#define PCI_REG_BASE 0x800000
#define PCI_REG_SIZE 0x40
+#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
-static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t pci4xx_cfgaddr_read(void *opaque, hwaddr addr,
+ unsigned size)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
+ PCIHostState *phb = PCI_HOST_BRIDGE(ppc4xx_pci);
- return ppc4xx_pci->pci_state.config_reg;
+ return phb->config_reg;
}
-static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
- &pci4xx_cfgaddr_readl,
- &pci4xx_cfgaddr_readl,
- &pci4xx_cfgaddr_readl,
-};
-
-static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static void pci4xx_cfgaddr_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
+ PCIHostState *phb = PCI_HOST_BRIDGE(ppc4xx_pci);
-#ifdef TARGET_WORDS_BIGENDIAN
- value = bswap32(value);
-#endif
-
- ppc4xx_pci->pci_state.config_reg = value & ~0x3;
+ phb->config_reg = value & ~0x3;
}
-static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
- &pci4xx_cfgaddr_writel,
- &pci4xx_cfgaddr_writel,
- &pci4xx_cfgaddr_writel,
-};
-
-static CPUReadMemoryFunc * const pci4xx_cfgdata_read[] = {
- &pci_host_data_readb,
- &pci_host_data_readw,
- &pci_host_data_readl,
-};
-
-static CPUWriteMemoryFunc * const pci4xx_cfgdata_write[] = {
- &pci_host_data_writeb,
- &pci_host_data_writew,
- &pci_host_data_writel,
+static const MemoryRegionOps pci4xx_cfgaddr_ops = {
+ .read = pci4xx_cfgaddr_read,
+ .write = pci4xx_cfgaddr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
-static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
{
struct PPC4xxPCIState *pci = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
- value = bswap32(value);
-#endif
-
/* We ignore all target attempts at PCI configuration, effectively
* assuming a bidirectional 1:1 mapping of PLB and PCI space. */
}
}
-static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
+static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
+ unsigned size)
{
struct PPC4xxPCIState *pci = opaque;
uint32_t value;
value = 0;
}
-#ifdef TARGET_WORDS_BIGENDIAN
- value = bswap32(value);
-#endif
-
return value;
}
-static CPUReadMemoryFunc * const pci_reg_read[] = {
- &ppc4xx_pci_reg_read4,
- &ppc4xx_pci_reg_read4,
- &ppc4xx_pci_reg_read4,
-};
-
-static CPUWriteMemoryFunc * const pci_reg_write[] = {
- &ppc4xx_pci_reg_write4,
- &ppc4xx_pci_reg_write4,
- &ppc4xx_pci_reg_write4,
+static const MemoryRegionOps pci_reg_ops = {
+ .read = ppc4xx_pci_reg_read4,
+ .write = ppc4xx_pci_reg_write4,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void ppc4xx_pci_reset(void *opaque)
qemu_irq *pci_irqs = opaque;
DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
+ if (irq_num < 0) {
+ fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
+ return;
+ }
qemu_set_irq(pci_irqs[irq_num], level);
}
-static void ppc4xx_pci_save(QEMUFile *f, void *opaque)
-{
- PPC4xxPCIState *controller = opaque;
- int i;
-
- pci_device_save(controller->pci_dev, f);
+static const VMStateDescription vmstate_pci_master_map = {
+ .name = "pci_master_map",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(la, struct PCIMasterMap),
+ VMSTATE_UINT32(ma, struct PCIMasterMap),
+ VMSTATE_UINT32(pcila, struct PCIMasterMap),
+ VMSTATE_UINT32(pciha, struct PCIMasterMap),
+ VMSTATE_END_OF_LIST()
+ }
+};
- for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) {
- qemu_put_be32s(f, &controller->pmm[i].la);
- qemu_put_be32s(f, &controller->pmm[i].ma);
- qemu_put_be32s(f, &controller->pmm[i].pcila);
- qemu_put_be32s(f, &controller->pmm[i].pciha);
+static const VMStateDescription vmstate_pci_target_map = {
+ .name = "pci_target_map",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(ms, struct PCITargetMap),
+ VMSTATE_UINT32(la, struct PCITargetMap),
+ VMSTATE_END_OF_LIST()
}
+};
- for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) {
- qemu_put_be32s(f, &controller->ptm[i].ms);
- qemu_put_be32s(f, &controller->ptm[i].la);
+static const VMStateDescription vmstate_ppc4xx_pci = {
+ .name = "ppc4xx_pci",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
+ vmstate_pci_master_map,
+ struct PCIMasterMap),
+ VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
+ vmstate_pci_target_map,
+ struct PCITargetMap),
+ VMSTATE_END_OF_LIST()
}
-}
+};
-static int ppc4xx_pci_load(QEMUFile *f, void *opaque, int version_id)
+/* XXX Interrupt acknowledge cycles not supported. */
+static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
{
- PPC4xxPCIState *controller = opaque;
+ PPC4xxPCIState *s;
+ PCIHostState *h;
+ PCIBus *b;
int i;
- if (version_id != 1)
- return -EINVAL;
-
- pci_device_load(controller->pci_dev, f);
+ h = PCI_HOST_BRIDGE(dev);
+ s = PPC4xx_PCI_HOST_BRIDGE(dev);
- for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) {
- qemu_get_be32s(f, &controller->pmm[i].la);
- qemu_get_be32s(f, &controller->pmm[i].ma);
- qemu_get_be32s(f, &controller->pmm[i].pcila);
- qemu_get_be32s(f, &controller->pmm[i].pciha);
+ for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
+ sysbus_init_irq(dev, &s->irq[i]);
}
- for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) {
- qemu_get_be32s(f, &controller->ptm[i].ms);
- qemu_get_be32s(f, &controller->ptm[i].la);
- }
+ b = pci_register_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
+ ppc4xx_pci_map_irq, s->irq, get_system_memory(),
+ get_system_io(), 0, 4);
+ h->bus = b;
+
+ pci_create_simple(b, 0, "ppc4xx-host-bridge");
+
+ /* XXX split into 2 memory regions, one for config space, one for regs */
+ memory_region_init(&s->container, "pci-container", PCI_ALL_SIZE);
+ memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops, h,
+ "pci-conf-idx", 4);
+ memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
+ "pci-conf-data", 4);
+ memory_region_init_io(&s->iomem, &pci_reg_ops, s,
+ "pci.reg", PCI_REG_SIZE);
+ memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
+ memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
+ memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
+ sysbus_init_mmio(dev, &s->container);
+ qemu_register_reset(ppc4xx_pci_reset, s);
return 0;
}
-/* XXX Interrupt acknowledge cycles not supported. */
-PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
- target_phys_addr_t config_space,
- target_phys_addr_t int_ack,
- target_phys_addr_t special_cycle,
- target_phys_addr_t registers)
+static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Host bridge";
+ k->vendor_id = PCI_VENDOR_ID_IBM;
+ k->device_id = PCI_DEVICE_ID_IBM_440GX;
+ k->class_id = PCI_CLASS_BRIDGE_OTHER;
+}
+
+static const TypeInfo ppc4xx_host_bridge_info = {
+ .name = "ppc4xx-host-bridge",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(PCIDevice),
+ .class_init = ppc4xx_host_bridge_class_init,
+};
+
+static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ k->init = ppc4xx_pcihost_initfn;
+ dc->vmsd = &vmstate_ppc4xx_pci;
+}
+
+static const TypeInfo ppc4xx_pcihost_info = {
+ .name = TYPE_PPC4xx_PCI_HOST_BRIDGE,
+ .parent = TYPE_PCI_HOST_BRIDGE,
+ .instance_size = sizeof(PPC4xxPCIState),
+ .class_init = ppc4xx_pcihost_class_init,
+};
+
+static void ppc4xx_pci_register_types(void)
{
- PPC4xxPCIState *controller;
- int index;
- static int ppc4xx_pci_id;
- uint8_t *pci_conf;
-
- controller = qemu_mallocz(sizeof(PPC4xxPCIState));
-
- controller->pci_state.bus = pci_register_bus(NULL, "pci",
- ppc4xx_pci_set_irq,
- ppc4xx_pci_map_irq,
- pci_irqs, 0, 4);
-
- controller->pci_dev = pci_register_device(controller->pci_state.bus,
- "host bridge", sizeof(PCIDevice),
- 0, NULL, NULL);
- pci_conf = controller->pci_dev->config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
- pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
-
- /* CFGADDR */
- index = cpu_register_io_memory(pci4xx_cfgaddr_read,
- pci4xx_cfgaddr_write, controller);
- if (index < 0)
- goto free;
- cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
-
- /* CFGDATA */
- index = cpu_register_io_memory(pci4xx_cfgdata_read,
- pci4xx_cfgdata_write,
- &controller->pci_state);
- if (index < 0)
- goto free;
- cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
-
- /* Internal registers */
- index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller);
- if (index < 0)
- goto free;
- cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
-
- qemu_register_reset(ppc4xx_pci_reset, controller);
-
- /* XXX load/save code not tested. */
- register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1,
- ppc4xx_pci_save, ppc4xx_pci_load, controller);
-
- return controller->pci_state.bus;
-
-free:
- printf("%s error\n", __func__);
- qemu_free(controller);
- return NULL;
+ type_register_static(&ppc4xx_pcihost_info);
+ type_register_static(&ppc4xx_host_bridge_info);
}
+
+type_init(ppc4xx_pci_register_types)
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