uint32_t gasket_time;
qemu_irq irq[4];
/* mmio maps */
- int reg;
+ MemoryRegion container;
+ MemoryRegion iomem;
};
typedef struct PPCE500PCIState PPCE500PCIState;
-static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
+static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
PPCE500PCIState *pci = opaque;
unsigned long win;
uint32_t value = 0;
+ int idx;
win = addr & 0xfe0;
case PPCE500_PCI_OW2:
case PPCE500_PCI_OW3:
case PPCE500_PCI_OW4:
+ idx = (addr >> 5) & 0x7;
switch (addr & 0xC) {
- case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break;
- case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break;
- case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break;
- case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break;
- default: break;
+ case PCI_POTAR:
+ value = pci->pob[idx].potar;
+ break;
+ case PCI_POTEAR:
+ value = pci->pob[idx].potear;
+ break;
+ case PCI_POWBAR:
+ value = pci->pob[idx].powbar;
+ break;
+ case PCI_POWAR:
+ value = pci->pob[idx].powar;
+ break;
+ default:
+ break;
}
break;
case PPCE500_PCI_IW3:
case PPCE500_PCI_IW2:
case PPCE500_PCI_IW1:
+ idx = ((addr >> 5) & 0x3) - 1;
switch (addr & 0xC) {
- case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break;
- case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break;
- case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break;
- case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break;
- default: break;
+ case PCI_PITAR:
+ value = pci->pib[idx].pitar;
+ break;
+ case PCI_PIWBAR:
+ value = pci->pib[idx].piwbar;
+ break;
+ case PCI_PIWBEAR:
+ value = pci->pib[idx].piwbear;
+ break;
+ case PCI_PIWAR:
+ value = pci->pib[idx].piwar;
+ break;
+ default:
+ break;
};
break;
return value;
}
-static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
- &pci_reg_read4,
- &pci_reg_read4,
- &pci_reg_read4,
-};
-
static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
PPCE500PCIState *pci = opaque;
unsigned long win;
+ int idx;
win = addr & 0xfe0;
pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
- __func__, value, win, addr);
+ __func__, (unsigned)value, win, addr);
switch (win) {
case PPCE500_PCI_OW1:
case PPCE500_PCI_OW2:
case PPCE500_PCI_OW3:
case PPCE500_PCI_OW4:
+ idx = (addr >> 5) & 0x7;
switch (addr & 0xC) {
- case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break;
- case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break;
- case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break;
- case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break;
- default: break;
+ case PCI_POTAR:
+ pci->pob[idx].potar = value;
+ break;
+ case PCI_POTEAR:
+ pci->pob[idx].potear = value;
+ break;
+ case PCI_POWBAR:
+ pci->pob[idx].powbar = value;
+ break;
+ case PCI_POWAR:
+ pci->pob[idx].powar = value;
+ break;
+ default:
+ break;
};
break;
case PPCE500_PCI_IW3:
case PPCE500_PCI_IW2:
case PPCE500_PCI_IW1:
+ idx = ((addr >> 5) & 0x3) - 1;
switch (addr & 0xC) {
- case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break;
- case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break;
- case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break;
- case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break;
- default: break;
+ case PCI_PITAR:
+ pci->pib[idx].pitar = value;
+ break;
+ case PCI_PIWBAR:
+ pci->pib[idx].piwbar = value;
+ break;
+ case PCI_PIWBEAR:
+ pci->pib[idx].piwbear = value;
+ break;
+ case PCI_PIWAR:
+ pci->pib[idx].piwar = value;
+ break;
+ default:
+ break;
};
break;
};
}
-static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
- &pci_reg_write4,
- &pci_reg_write4,
- &pci_reg_write4,
+static const MemoryRegionOps e500_pci_reg_ops = {
+ .read = pci_reg_read4,
+ .write = pci_reg_write4,
+ .endianness = DEVICE_BIG_ENDIAN,
};
static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
}
};
-static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
-{
- PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
- PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h);
-
- sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem);
- sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem);
- cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
- s->reg);
-}
-
-static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
-{
- PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
-
- sysbus_del_memory(dev, &h->conf_mem);
- sysbus_del_memory(dev, &h->data_mem);
- cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
- IO_MEM_UNASSIGNED);
-}
-
#include "exec-memory.h"
static int e500_pcihost_initfn(SysBusDevice *dev)
pci_create_simple(b, 0, "e500-host-bridge");
+ memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
"pci-conf-idx", 4);
memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
"pci-conf-data", 4);
- s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
- DEVICE_BIG_ENDIAN);
- sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);
+ memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
+ "pci.reg", PCIE500_REG_SIZE);
+ memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
+ memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
+ memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
+ sysbus_init_mmio(dev, &s->container);
return 0;
}
projects / mirror_qemu.git / blobdiff