#include "ssi.h"
#include "qemu-timer.h"
#include "qemu-char.h"
+#include "blockdev.h"
static struct {
target_phys_addr_t io_base;
break;
default: /* Read-write registers */
- if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
+ if (!(addr & 3)) {
s->pm_regs[addr >> 2] = value;
break;
}
{
s->sssr &= ~(0xf << 12); /* Clear RFL */
s->sssr &= ~(0xf << 8); /* Clear TFL */
+ s->sssr &= ~SSSR_TFS;
s->sssr &= ~SSSR_TNF;
if (s->enable) {
s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
s->sssr |= SSSR_RFS;
else
s->sssr &= ~SSSR_RFS;
- if (0 <= SSCR1_TFT(s->sscr[1]))
- s->sssr |= SSSR_TFS;
- else
- s->sssr &= ~SSSR_TFS;
if (s->rx_level)
s->sssr |= SSSR_RNE;
else
s->sssr &= ~SSSR_RNE;
+ /* TX FIFO is never filled, so it is always in underrun
+ condition if SSP is enabled */
+ s->sssr |= SSSR_TFS;
s->sssr |= SSSR_TNF;
}
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
- pxa2xx_ssp_writefn, s);
+ pxa2xx_ssp_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
- register_savevm("pxa2xx_ssp", -1, 0,
+ register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
s->bus = ssi_create_bus(&dev->qdev, "ssi");
pxa2xx_i2c_write,
};
-static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
-{
- PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
-
- qemu_put_be16s(f, &s->control);
- qemu_put_be16s(f, &s->status);
- qemu_put_8s(f, &s->ibmr);
- qemu_put_8s(f, &s->data);
-
- i2c_slave_save(f, &s->slave->i2c);
-}
-
-static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
-{
- PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
-
- if (version_id != 1)
- return -EINVAL;
-
- qemu_get_be16s(f, &s->control);
- qemu_get_be16s(f, &s->status);
- qemu_get_8s(f, &s->ibmr);
- qemu_get_8s(f, &s->data);
+static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
+ .name = "pxa2xx_i2c_slave",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
+ VMSTATE_END_OF_LIST()
+ }
+};
- i2c_slave_load(f, &s->slave->i2c);
- return 0;
-}
+static const VMStateDescription vmstate_pxa2xx_i2c = {
+ .name = "pxa2xx_i2c",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT16(control, PXA2xxI2CState),
+ VMSTATE_UINT16(status, PXA2xxI2CState),
+ VMSTATE_UINT8(ibmr, PXA2xxI2CState),
+ VMSTATE_UINT8(data, PXA2xxI2CState),
+ VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
+ vmstate_pxa2xx_i2c, PXA2xxI2CSlaveState *),
+ VMSTATE_END_OF_LIST()
+ }
+};
static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
{
s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK);
iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
- pxa2xx_i2c_writefn, s);
+ pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base & ~region_size,
region_size + 1, iomemtype);
- register_savevm("pxa2xx_i2c", base, 1,
- pxa2xx_i2c_save, pxa2xx_i2c_load, s);
+ vmstate_register(NULL, base, &vmstate_pxa2xx_i2c, s);
return s;
}
pxa2xx_i2s_reset(s);
iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
- pxa2xx_i2s_writefn, s);
+ pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100000, iomemtype);
- register_savevm("pxa2xx_i2s", base, 0,
+ register_savevm(NULL, "pxa2xx_i2s", base, 0,
pxa2xx_i2s_save, pxa2xx_i2s_load, s);
return s;
s->control[0] = value;
if (!(value & (1 << 4))) /* RXE */
s->rx_len = s->rx_start = 0;
- if (!(value & (1 << 3))) /* TXE */
- /* Nop */;
+ if (!(value & (1 << 3))) { /* TXE */
+ /* Nop */
+ }
s->enable = value & 1; /* ITR */
if (!s->enable)
s->status[0] = 0;
pxa2xx_fir_reset(s);
iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
- pxa2xx_fir_writefn, s);
+ pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
if (chr)
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
pxa2xx_fir_rx, pxa2xx_fir_event, s);
- register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
+ register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
+ pxa2xx_fir_load, s);
return s;
}
/* SDRAM & Internal Memory Storage */
cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
- sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
+ sdram_size, qemu_ram_alloc(NULL, "pxa270.sdram",
+ sdram_size) | IO_MEM_RAM);
cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
- 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
+ 0x40000, qemu_ram_alloc(NULL, "pxa270.internal",
+ 0x40000) | IO_MEM_RAM);
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
for (i = 0; pxa270_serial[i].io_base; i ++)
if (serial_hds[i])
+#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(pxa270_serial[i].io_base, 2,
s->pic[pxa270_serial[i].irqn], 14857000/16,
- serial_hds[i], 1);
+ serial_hds[i], 1, 1);
+#else
+ serial_mm_init(pxa270_serial[i].io_base, 2,
+ s->pic[pxa270_serial[i].irqn], 14857000/16,
+ serial_hds[i], 1, 0);
+#endif
else
break;
if (serial_hds[i])
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
- pxa2xx_cm_writefn, s);
+ pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
- register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
+ register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
- pxa2xx_mm_writefn, s);
+ pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
- register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
+ register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
s->pm_base = 0x40f00000;
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
- pxa2xx_pm_writefn, s);
+ pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
- register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
+ register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
for (i = 0; pxa27x_ssp[i].io_base; i ++);
s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
}
if (usb_enabled) {
- usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
+ sysbus_create_simple("sysbus-ohci", 0x4c000000,
+ s->pic[PXA2XX_PIC_USBH1]);
}
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
- pxa2xx_rtc_writefn, s);
+ pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
pxa2xx_rtc_init(s);
- register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
+ register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
+ pxa2xx_rtc_load, s);
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
/* SDRAM & Internal Memory Storage */
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
- qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
+ qemu_ram_alloc(NULL, "pxa255.sdram",
+ sdram_size) | IO_MEM_RAM);
cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
- qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
+ qemu_ram_alloc(NULL, "pxa255.internal",
+ PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
s->pic[PXA2XX_PIC_MMC], s->dma);
for (i = 0; pxa255_serial[i].io_base; i ++)
- if (serial_hds[i])
+ if (serial_hds[i]) {
+#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(pxa255_serial[i].io_base, 2,
s->pic[pxa255_serial[i].irqn], 14745600/16,
- serial_hds[i], 1);
- else
+ serial_hds[i], 1, 1);
+#else
+ serial_mm_init(pxa255_serial[i].io_base, 2,
+ s->pic[pxa255_serial[i].irqn], 14745600/16,
+ serial_hds[i], 1, 0);
+#endif
+ } else {
break;
+ }
if (serial_hds[i])
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
s->dma, serial_hds[i]);
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
- pxa2xx_cm_writefn, s);
+ pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
- register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
+ register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
- pxa2xx_mm_writefn, s);
+ pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
- register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
+ register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
s->pm_base = 0x40f00000;
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
- pxa2xx_pm_writefn, s);
+ pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
- register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
+ register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
for (i = 0; pxa255_ssp[i].io_base; i ++);
s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
}
if (usb_enabled) {
- usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
+ sysbus_create_simple("sysbus-ohci", 0x4c000000,
+ s->pic[PXA2XX_PIC_USBH1]);
}
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
- pxa2xx_rtc_writefn, s);
+ pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
pxa2xx_rtc_init(s);
- register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
+ register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
+ pxa2xx_rtc_load, s);
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
projects / mirror_qemu.git / blobdiff