#include "hw.h"
#include "pxa.h"
#include "sd.h"
+#include "qdev.h"
-struct pxa2xx_mmci_s {
- target_phys_addr_t base;
+struct PXA2xxMMCIState {
+ MemoryRegion iomem;
qemu_irq irq;
- void *dma;
+ qemu_irq rx_dma;
+ qemu_irq tx_dma;
SDState *card;
#define PRTBUF_PRT_BUF (1 << 0)
/* Route internal interrupt lines to the global IC and DMA */
-static void pxa2xx_mmci_int_update(struct pxa2xx_mmci_s *s)
+static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
{
uint32_t mask = s->intmask;
if (s->cmdat & CMDAT_DMA_EN) {
mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
- pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
- PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ));
- pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
- PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ));
+ qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
+ qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
}
qemu_set_irq(s->irq, !!(s->intreq & ~mask));
}
-static void pxa2xx_mmci_fifo_update(struct pxa2xx_mmci_s *s)
+static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
{
if (!s->active)
return;
pxa2xx_mmci_int_update(s);
}
-static void pxa2xx_mmci_wakequeues(struct pxa2xx_mmci_s *s)
+static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
{
int rsplen, i;
- struct sd_request_s request;
+ SDRequest request;
uint8_t response[16];
s->active = 1;
static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
{
- struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
+ PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
uint32_t ret;
- offset -= s->base;
switch (offset) {
case MMC_STRPCL:
case MMC_BLKS_REM:
return s->numblk;
default:
- cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
- __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
return 0;
static void pxa2xx_mmci_write(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
- struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
- offset -= s->base;
+ PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
switch (offset) {
case MMC_STRPCL:
break;
default:
- cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
- __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
}
static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
{
- struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
+ PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 1;
return pxa2xx_mmci_read(opaque, offset);
}
static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
{
- struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
+ PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 2;
return pxa2xx_mmci_read(opaque, offset);
}
static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
{
- struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
+ PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 4;
return pxa2xx_mmci_read(opaque, offset);
}
-static CPUReadMemoryFunc *pxa2xx_mmci_readfn[] = {
- pxa2xx_mmci_readb,
- pxa2xx_mmci_readh,
- pxa2xx_mmci_readw
-};
-
static void pxa2xx_mmci_writeb(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
- struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
+ PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 1;
pxa2xx_mmci_write(opaque, offset, value);
}
static void pxa2xx_mmci_writeh(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
- struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
+ PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 2;
pxa2xx_mmci_write(opaque, offset, value);
}
static void pxa2xx_mmci_writew(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
- struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
+ PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 4;
pxa2xx_mmci_write(opaque, offset, value);
}
-static CPUWriteMemoryFunc *pxa2xx_mmci_writefn[] = {
- pxa2xx_mmci_writeb,
- pxa2xx_mmci_writeh,
- pxa2xx_mmci_writew
+static const MemoryRegionOps pxa2xx_mmci_ops = {
+ .old_mmio = {
+ .read = { pxa2xx_mmci_readb,
+ pxa2xx_mmci_readh,
+ pxa2xx_mmci_readw, },
+ .write = { pxa2xx_mmci_writeb,
+ pxa2xx_mmci_writeh,
+ pxa2xx_mmci_writew, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void pxa2xx_mmci_save(QEMUFile *f, void *opaque)
{
- struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
+ PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
int i;
qemu_put_be32s(f, &s->status);
static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
{
- struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque;
+ PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
int i;
qemu_get_be32s(f, &s->status);
return 0;
}
-struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
- BlockDriverState *bd, qemu_irq irq, void *dma)
+PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ BlockDriverState *bd, qemu_irq irq,
+ qemu_irq rx_dma, qemu_irq tx_dma)
{
- int iomemtype;
- struct pxa2xx_mmci_s *s;
+ PXA2xxMMCIState *s;
- s = (struct pxa2xx_mmci_s *) qemu_mallocz(sizeof(struct pxa2xx_mmci_s));
- s->base = base;
+ s = (PXA2xxMMCIState *) g_malloc0(sizeof(PXA2xxMMCIState));
s->irq = irq;
- s->dma = dma;
+ s->rx_dma = rx_dma;
+ s->tx_dma = tx_dma;
- iomemtype = cpu_register_io_memory(0, pxa2xx_mmci_readfn,
- pxa2xx_mmci_writefn, s);
- cpu_register_physical_memory(base, 0x00100000, iomemtype);
+ memory_region_init_io(&s->iomem, &pxa2xx_mmci_ops, s,
+ "pxa2xx-mmci", 0x00100000);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
/* Instantiate the actual storage */
- s->card = sd_init(bd);
+ s->card = sd_init(bd, 0);
- register_savevm("pxa2xx_mmci", 0, 0,
+ register_savevm(NULL, "pxa2xx_mmci", 0, 0,
pxa2xx_mmci_save, pxa2xx_mmci_load, s);
return s;
}
-void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
+void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
qemu_irq coverswitch)
{
sd_set_cb(s->card, readonly, coverswitch);
projects / mirror_qemu.git / blobdiff