static PCIQXLDevice *qxl0;
static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
-static void qxl_destroy_primary(PCIQXLDevice *d);
+static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
static void qxl_reset_memslots(PCIQXLDevice *d);
static void qxl_reset_surfaces(PCIQXLDevice *d);
static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
struct QXLRect *area, struct QXLRect *dirty_rects,
uint32_t num_dirty_rects,
- uint32_t clear_dirty_region)
+ uint32_t clear_dirty_region,
+ qxl_async_io async)
{
- qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, dirty_rects,
- num_dirty_rects, clear_dirty_region);
+ if (async == QXL_SYNC) {
+ qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
+ dirty_rects, num_dirty_rects, clear_dirty_region);
+ } else {
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+ spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
+ clear_dirty_region, 0);
+#else
+ abort();
+#endif
+ }
}
-void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id)
+static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
+ uint32_t id)
{
qemu_mutex_lock(&qxl->track_lock);
- PANIC_ON(id >= NUM_SURFACES);
- qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
qxl->guest_surfaces.cmds[id] = 0;
qxl->guest_surfaces.count--;
qemu_mutex_unlock(&qxl->track_lock);
}
+static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
+ qxl_async_io async)
+{
+ if (async) {
+#if SPICE_INTERFACE_QXL_MINOR < 1
+ abort();
+#else
+ spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id,
+ (uint64_t)id);
+#endif
+ } else {
+ qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
+ qxl_spice_destroy_surface_wait_complete(qxl, id);
+ }
+}
+
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
+{
+ spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 0);
+}
+#endif
+
void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
uint32_t count)
{
qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
}
-void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl)
+static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
{
qemu_mutex_lock(&qxl->track_lock);
- qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
qxl->guest_surfaces.count = 0;
qemu_mutex_unlock(&qxl->track_lock);
}
+static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
+{
+ if (async) {
+#if SPICE_INTERFACE_QXL_MINOR < 1
+ abort();
+#else
+ spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 0);
+#endif
+ } else {
+ qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
+ qxl_spice_destroy_surfaces_complete(qxl);
+ }
+}
+
void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
{
qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
static void init_qxl_rom(PCIQXLDevice *d)
{
- QXLRom *rom = qemu_get_ram_ptr(d->rom_offset);
+ QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
QXLModes *modes = (QXLModes *)(rom + 1);
uint32_t ram_header_size;
uint32_t surface0_area_size;
}
/* can be called from spice server thread context */
-static void qxl_set_dirty(ram_addr_t addr, ram_addr_t end)
+static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
{
while (addr < end) {
- cpu_physical_memory_set_dirty(addr);
+ memory_region_set_dirty(mr, addr);
addr += TARGET_PAGE_SIZE;
}
}
static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
{
- ram_addr_t addr = qxl->rom_offset;
- qxl_set_dirty(addr, addr + qxl->rom_size);
+ qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
}
/* called from spice server thread context only */
static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
{
- ram_addr_t addr = qxl->vga.vram_offset;
void *base = qxl->vga.vram_ptr;
intptr_t offset;
offset = ptr - base;
offset &= ~(TARGET_PAGE_SIZE-1);
assert(offset < qxl->vga.vram_size);
- qxl_set_dirty(addr + offset, addr + offset + TARGET_PAGE_SIZE);
+ qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
}
/* can be called from spice server thread context */
static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
{
- ram_addr_t addr = qxl->vga.vram_offset + qxl->shadow_rom.ram_header_offset;
- ram_addr_t end = qxl->vga.vram_offset + qxl->vga.vram_size;
- qxl_set_dirty(addr, end);
+ ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
+ ram_addr_t end = qxl->vga.vram_size;
+ qxl_set_dirty(&qxl->vga.vram, addr, end);
}
/*
return ret;
}
+static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
+
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+
+/* called from spice server thread context only */
+static void interface_async_complete(QXLInstance *sin, uint64_t cookie)
+{
+ PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
+ uint32_t current_async;
+
+ qemu_mutex_lock(&qxl->async_lock);
+ current_async = qxl->current_async;
+ qxl->current_async = QXL_UNDEFINED_IO;
+ qemu_mutex_unlock(&qxl->async_lock);
+
+ dprint(qxl, 2, "async_complete: %d (%ld) done\n", current_async, cookie);
+ switch (current_async) {
+ case QXL_IO_CREATE_PRIMARY_ASYNC:
+ qxl_create_guest_primary_complete(qxl);
+ break;
+ case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
+ qxl_spice_destroy_surfaces_complete(qxl);
+ break;
+ case QXL_IO_DESTROY_SURFACE_ASYNC:
+ qxl_spice_destroy_surface_wait_complete(qxl, (uint32_t)cookie);
+ break;
+ }
+ qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
+}
+
+#endif
+
static const QXLInterface qxl_interface = {
.base.type = SPICE_INTERFACE_QXL,
.base.description = "qxl gpu",
.req_cursor_notification = interface_req_cursor_notification,
.notify_update = interface_notify_update,
.flush_resources = interface_flush_resources,
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+ .async_complete = interface_async_complete,
+#endif
};
static void qxl_enter_vga_mode(PCIQXLDevice *d)
return;
}
dprint(d, 1, "%s\n", __FUNCTION__);
- qxl_destroy_primary(d);
+ qxl_destroy_primary(d, QXL_SYNC);
}
static void qxl_set_irq(PCIQXLDevice *d)
qxl_ring_set_dirty(d);
}
-static void qxl_write_config(PCIDevice *d, uint32_t address,
- uint32_t val, int len)
-{
- PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, d);
- VGACommonState *vga = &qxl->vga;
-
- vga_dirty_log_stop(vga);
- pci_default_write_config(d, address, val, len);
- if (vga->map_addr && qxl->pci.io_regions[0].addr == -1) {
- vga->map_addr = 0;
- }
- vga_dirty_log_start(vga);
-}
-
static void qxl_check_state(PCIQXLDevice *d)
{
QXLRam *ram = d->ram;
- assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
- assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
+ assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
+ assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
}
static void qxl_reset_state(PCIQXLDevice *d)
{
- QXLRam *ram = d->ram;
QXLRom *rom = d->rom;
- assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
- assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
+ qxl_check_state(d);
d->shadow_rom.update_id = cpu_to_le32(0);
*rom = d->shadow_rom;
qxl_rom_set_dirty(d);
if (qxl->mode != QXL_MODE_VGA) {
dprint(qxl, 1, "%s\n", __FUNCTION__);
- qxl_destroy_primary(qxl);
+ qxl_destroy_primary(qxl, QXL_SYNC);
qxl_soft_reset(qxl);
}
vga_ioport_write(opaque, addr, val);
}
-static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta)
+static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
+ qxl_async_io async)
{
static const int regions[] = {
QXL_RAM_RANGE_INDEX,
switch (pci_region) {
case QXL_RAM_RANGE_INDEX:
- virt_start = (intptr_t)qemu_get_ram_ptr(d->vga.vram_offset);
+ virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
break;
case QXL_VRAM_RANGE_INDEX:
- virt_start = (intptr_t)qemu_get_ram_ptr(d->vram_offset);
+ virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
break;
default:
/* should not happen */
__FUNCTION__, memslot.slot_id,
memslot.virt_start, memslot.virt_end);
- qemu_spice_add_memslot(&d->ssd, &memslot);
+ qemu_spice_add_memslot(&d->ssd, &memslot, async);
d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
d->guest_slots[slot_id].delta = delta;
{
dprint(d, 1, "%s:\n", __FUNCTION__);
d->mode = QXL_MODE_UNDEFINED;
- qxl_spice_destroy_surfaces(d);
+ qxl_spice_destroy_surfaces(d, QXL_SYNC);
}
/* called from spice server thread context only */
}
}
-static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm)
+static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
+{
+ /* for local rendering */
+ qxl_render_resize(qxl);
+}
+
+static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
+ qxl_async_io async)
{
QXLDevSurfaceCreate surface;
QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
qxl->mode = QXL_MODE_NATIVE;
qxl->cmdflags = 0;
- qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface);
+ qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
- /* for local rendering */
- qxl_render_resize(qxl);
+ if (async == QXL_SYNC) {
+ qxl_create_guest_primary_complete(qxl);
+ }
}
-static void qxl_destroy_primary(PCIQXLDevice *d)
+/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
+ * done (in QXL_SYNC case), 0 otherwise. */
+static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
{
if (d->mode == QXL_MODE_UNDEFINED) {
- return;
+ return 0;
}
dprint(d, 1, "%s\n", __FUNCTION__);
d->mode = QXL_MODE_UNDEFINED;
- qemu_spice_destroy_primary_surface(&d->ssd, 0);
+ qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
+ return 1;
}
static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
}
d->guest_slots[0].slot = slot;
- qxl_add_memslot(d, 0, devmem);
+ qxl_add_memslot(d, 0, devmem, QXL_SYNC);
d->guest_primary.surface = surface;
- qxl_create_guest_primary(d, 0);
+ qxl_create_guest_primary(d, 0, QXL_SYNC);
d->mode = QXL_MODE_COMPAT;
d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
qxl_rom_set_dirty(d);
}
-static void ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void ioport_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
PCIQXLDevice *d = opaque;
- uint32_t io_port = addr - d->io_base;
+ uint32_t io_port = addr;
+ qxl_async_io async = QXL_SYNC;
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+ uint32_t orig_io_port = io_port;
+#endif
switch (io_port) {
case QXL_IO_RESET:
case QXL_IO_CREATE_PRIMARY:
case QXL_IO_UPDATE_IRQ:
case QXL_IO_LOG:
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+ case QXL_IO_MEMSLOT_ADD_ASYNC:
+ case QXL_IO_CREATE_PRIMARY_ASYNC:
+#endif
break;
default:
if (d->mode != QXL_MODE_VGA) {
}
dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
__func__, io_port, io_port_to_string(io_port));
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+ /* be nice to buggy guest drivers */
+ if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
+ io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
+ qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
+ }
+#endif
return;
}
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+ /* we change the io_port to avoid ifdeffery in the main switch */
+ orig_io_port = io_port;
+ switch (io_port) {
+ case QXL_IO_UPDATE_AREA_ASYNC:
+ io_port = QXL_IO_UPDATE_AREA;
+ goto async_common;
+ case QXL_IO_MEMSLOT_ADD_ASYNC:
+ io_port = QXL_IO_MEMSLOT_ADD;
+ goto async_common;
+ case QXL_IO_CREATE_PRIMARY_ASYNC:
+ io_port = QXL_IO_CREATE_PRIMARY;
+ goto async_common;
+ case QXL_IO_DESTROY_PRIMARY_ASYNC:
+ io_port = QXL_IO_DESTROY_PRIMARY;
+ goto async_common;
+ case QXL_IO_DESTROY_SURFACE_ASYNC:
+ io_port = QXL_IO_DESTROY_SURFACE_WAIT;
+ goto async_common;
+ case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
+ io_port = QXL_IO_DESTROY_ALL_SURFACES;
+ goto async_common;
+ case QXL_IO_FLUSH_SURFACES_ASYNC:
+async_common:
+ async = QXL_ASYNC;
+ qemu_mutex_lock(&d->async_lock);
+ if (d->current_async != QXL_UNDEFINED_IO) {
+ qxl_guest_bug(d, "%d async started before last (%d) complete",
+ io_port, d->current_async);
+ qemu_mutex_unlock(&d->async_lock);
+ return;
+ }
+ d->current_async = orig_io_port;
+ qemu_mutex_unlock(&d->async_lock);
+ dprint(d, 2, "start async %d (%"PRId64")\n", io_port, val);
+ break;
+ default:
+ break;
+ }
+#endif
+
switch (io_port) {
case QXL_IO_UPDATE_AREA:
{
QXLRect update = d->ram->update_area;
qxl_spice_update_area(d, d->ram->update_surface,
- &update, NULL, 0, 0);
+ &update, NULL, 0, 0, async);
break;
}
case QXL_IO_NOTIFY_CMD:
d->oom_running = 0;
break;
case QXL_IO_SET_MODE:
- dprint(d, 1, "QXL_SET_MODE %d\n", val);
+ dprint(d, 1, "QXL_SET_MODE %d\n", (int)val);
qxl_set_mode(d, val, 0);
break;
case QXL_IO_LOG:
break;
}
d->guest_slots[val].slot = d->ram->mem_slot;
- qxl_add_memslot(d, val, 0);
+ qxl_add_memslot(d, val, 0, async);
break;
case QXL_IO_MEMSLOT_DEL:
if (val >= NUM_MEMSLOTS) {
break;
case QXL_IO_CREATE_PRIMARY:
if (val != 0) {
- qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY: val != 0");
- break;
+ qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
+ async);
+ goto cancel_async;
}
- dprint(d, 1, "QXL_IO_CREATE_PRIMARY\n");
+ dprint(d, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async);
d->guest_primary.surface = d->ram->create_surface;
- qxl_create_guest_primary(d, 0);
+ qxl_create_guest_primary(d, 0, async);
break;
case QXL_IO_DESTROY_PRIMARY:
if (val != 0) {
- qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY: val != 0");
- break;
+ qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
+ async);
+ goto cancel_async;
+ }
+ dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async,
+ qxl_mode_to_string(d->mode));
+ if (!qxl_destroy_primary(d, async)) {
+ dprint(d, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
+ qxl_mode_to_string(d->mode));
+ goto cancel_async;
}
- dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (%s)\n", qxl_mode_to_string(d->mode));
- qxl_destroy_primary(d);
break;
case QXL_IO_DESTROY_SURFACE_WAIT:
- qxl_spice_destroy_surface_wait(d, val);
+ if (val >= NUM_SURFACES) {
+ qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
+ "%d >= NUM_SURFACES", async, val);
+ goto cancel_async;
+ }
+ qxl_spice_destroy_surface_wait(d, val, async);
+ break;
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+ case QXL_IO_FLUSH_RELEASE: {
+ QXLReleaseRing *ring = &d->ram->release_ring;
+ if (ring->prod - ring->cons + 1 == ring->num_items) {
+ fprintf(stderr,
+ "ERROR: no flush, full release ring [p%d,%dc]\n",
+ ring->prod, ring->cons);
+ }
+ qxl_push_free_res(d, 1 /* flush */);
+ dprint(d, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
+ qxl_mode_to_string(d->mode), d->guest_surfaces.count,
+ d->num_free_res, d->last_release);
+ break;
+ }
+ case QXL_IO_FLUSH_SURFACES_ASYNC:
+ dprint(d, 1, "QXL_IO_FLUSH_SURFACES_ASYNC"
+ " (%"PRId64") (%s, s#=%d, res#=%d)\n",
+ val, qxl_mode_to_string(d->mode), d->guest_surfaces.count,
+ d->num_free_res);
+ qxl_spice_flush_surfaces_async(d);
break;
+#endif
case QXL_IO_DESTROY_ALL_SURFACES:
- qxl_spice_destroy_surfaces(d);
+ d->mode = QXL_MODE_UNDEFINED;
+ qxl_spice_destroy_surfaces(d, async);
break;
default:
fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
abort();
}
+ return;
+cancel_async:
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+ if (async) {
+ qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
+ qemu_mutex_lock(&d->async_lock);
+ d->current_async = QXL_UNDEFINED_IO;
+ qemu_mutex_unlock(&d->async_lock);
+ }
+#else
+ return;
+#endif
}
-static uint32_t ioport_read(void *opaque, uint32_t addr)
+static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
PCIQXLDevice *d = opaque;
return 0xff;
}
-static void qxl_map(PCIDevice *pci, int region_num,
- pcibus_t addr, pcibus_t size, int type)
-{
- static const char *names[] = {
- [ QXL_IO_RANGE_INDEX ] = "ioports",
- [ QXL_RAM_RANGE_INDEX ] = "devram",
- [ QXL_ROM_RANGE_INDEX ] = "rom",
- [ QXL_VRAM_RANGE_INDEX ] = "vram",
- };
- PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, pci);
-
- dprint(qxl, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__,
- region_num, names[region_num], addr, size);
-
- switch (region_num) {
- case QXL_IO_RANGE_INDEX:
- register_ioport_write(addr, size, 1, ioport_write, pci);
- register_ioport_read(addr, size, 1, ioport_read, pci);
- qxl->io_base = addr;
- break;
- case QXL_RAM_RANGE_INDEX:
- cpu_register_physical_memory(addr, size, qxl->vga.vram_offset | IO_MEM_RAM);
- qxl->vga.map_addr = addr;
- qxl->vga.map_end = addr + size;
- if (qxl->id == 0) {
- vga_dirty_log_start(&qxl->vga);
- }
- break;
- case QXL_ROM_RANGE_INDEX:
- cpu_register_physical_memory(addr, size, qxl->rom_offset | IO_MEM_ROM);
- break;
- case QXL_VRAM_RANGE_INDEX:
- cpu_register_physical_memory(addr, size, qxl->vram_offset | IO_MEM_RAM);
- break;
- }
-}
+static const MemoryRegionOps qxl_io_ops = {
+ .read = ioport_read,
+ .write = ioport_write,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
static void pipe_read(void *opaque)
{
* to make sure they are saved */
/* FIXME #1: should go out during "live" stage */
/* FIXME #2: we only need to save the areas which are actually used */
- ram_addr_t vram_addr = qxl->vram_offset;
- ram_addr_t surface0_addr = qxl->vga.vram_offset + qxl->shadow_rom.draw_area_offset;
- qxl_set_dirty(vram_addr, vram_addr + qxl->vram_size);
- qxl_set_dirty(surface0_addr, surface0_addr + qxl->shadow_rom.surface0_area_size);
+ qxl_set_dirty(&qxl->vram_bar, 0, qxl->vram_size);
+ qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
+ qxl->shadow_rom.surface0_area_size);
}
}
qxl->num_memslots = NUM_MEMSLOTS;
qxl->num_surfaces = NUM_SURFACES;
qemu_mutex_init(&qxl->track_lock);
+ qemu_mutex_init(&qxl->async_lock);
+ qxl->current_async = QXL_UNDEFINED_IO;
switch (qxl->revision) {
case 1: /* spice 0.4 -- qxl-1 */
pci_device_rev = QXL_REVISION_STABLE_V04;
break;
case 2: /* spice 0.6 -- qxl-2 */
- default:
pci_device_rev = QXL_REVISION_STABLE_V06;
break;
+#if SPICE_INTERFACE_QXL_MINOR >= 1
+ case 3: /* qxl-3 */
+#endif
+ default:
+ pci_device_rev = QXL_DEFAULT_REVISION;
+ break;
}
pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
qxl->rom_size = qxl_rom_size();
- qxl->rom_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vrom", qxl->rom_size);
+ memory_region_init_ram(&qxl->rom_bar, &qxl->pci.qdev, "qxl.vrom",
+ qxl->rom_size);
init_qxl_rom(qxl);
init_qxl_ram(qxl);
qxl->vram_size = 4096;
}
qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
- qxl->vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vram", qxl->vram_size);
+ memory_region_init_ram(&qxl->vram_bar, &qxl->pci.qdev, "qxl.vram",
+ qxl->vram_size);
io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
if (qxl->revision == 1) {
io_size = 8;
}
+ memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
+ "qxl-ioports", io_size);
+ if (qxl->id == 0) {
+ vga_dirty_log_start(&qxl->vga);
+ }
+
+
pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
- io_size, PCI_BASE_ADDRESS_SPACE_IO, qxl_map);
+ PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
- qxl->rom_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
- qxl_map);
+ PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
- qxl->vga.vram_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
- qxl_map);
+ PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
- pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, qxl->vram_size,
- PCI_BASE_ADDRESS_SPACE_MEMORY, qxl_map);
+ pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
+ PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram_bar);
qxl->ssd.qxl.base.sif = &qxl_interface.base;
qxl->ssd.qxl.id = qxl->id;
ram_size = 16 * 1024 * 1024;
}
qxl->vga.vram_size = ram_size;
- qxl->vga.vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vgavram",
- qxl->vga.vram_size);
- qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset);
+ memory_region_init_ram(&qxl->vga.vram, &qxl->pci.qdev, "qxl.vgavram",
+ qxl->vga.vram_size);
+ qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
return qxl_init_common(qxl);
}
if (!d->guest_slots[i].active) {
continue;
}
- qxl_add_memslot(d, i, 0);
+ qxl_add_memslot(d, i, 0, QXL_SYNC);
}
- qxl_create_guest_primary(d, 1);
+ qxl_create_guest_primary(d, 1, QXL_SYNC);
/* replay surface-create and cursor-set commands */
- cmds = qemu_mallocz(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
+ cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
for (in = 0, out = 0; in < NUM_SURFACES; in++) {
if (d->guest_surfaces.cmds[in] == 0) {
continue;
cmds[out].group_id = MEMSLOT_GROUP_GUEST;
out++;
qxl_spice_loadvm_commands(d, cmds, out);
- qemu_free(cmds);
+ g_free(cmds);
break;
case QXL_MODE_COMPAT:
.qdev.vmsd = &qxl_vmstate,
.no_hotplug = 1,
.init = qxl_init_primary,
- .config_write = qxl_write_config,
.romfile = "vgabios-qxl.bin",
.vendor_id = REDHAT_PCI_VENDOR_ID,
.device_id = QXL_DEVICE_ID_STABLE,
.class_id = PCI_CLASS_DISPLAY_VGA,
.qdev.props = (Property[]) {
- DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
- DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
- DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
+ DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
+ 64 * 1024 * 1024),
+ DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size,
+ 64 * 1024 * 1024),
+ DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
+ QXL_DEFAULT_REVISION),
DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
.device_id = QXL_DEVICE_ID_STABLE,
.class_id = PCI_CLASS_DISPLAY_OTHER,
.qdev.props = (Property[]) {
- DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
- DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
- DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
+ DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
+ 64 * 1024 * 1024),
+ DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size,
+ 64 * 1024 * 1024),
+ DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
+ QXL_DEFAULT_REVISION),
DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
projects / mirror_qemu.git / blobdiff