#include "devices.h"
#include "sysemu.h"
#include "boards.h"
-#include "pci.h"
-#include "net.h"
+#include "pci/pci.h"
+#include "net/net.h"
#include "sh7750_regs.h"
#include "ide.h"
#include "loader.h"
#include "usb.h"
#include "flash.h"
#include "blockdev.h"
+#include "exec/address-spaces.h"
#define FLASH_BASE 0x00000000
#define FLASH_SIZE 0x02000000
/* output pin */
qemu_irq irl;
+ MemoryRegion iomem;
} r2d_fpga_t;
enum r2d_fpga_irq {
update_irl(fpga);
}
-static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
+static uint32_t r2d_fpga_read(void *opaque, hwaddr addr)
{
r2d_fpga_t *s = opaque;
}
static void
-r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value)
{
r2d_fpga_t *s = opaque;
}
}
-static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
- r2d_fpga_read,
- r2d_fpga_read,
- NULL,
+static const MemoryRegionOps r2d_fpga_ops = {
+ .old_mmio = {
+ .read = { r2d_fpga_read, r2d_fpga_read, NULL, },
+ .write = { r2d_fpga_write, r2d_fpga_write, NULL, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
- r2d_fpga_write,
- r2d_fpga_write,
- NULL,
-};
-
-static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
+static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
+ hwaddr base, qemu_irq irl)
{
- int iomemtype;
r2d_fpga_t *s;
- s = qemu_mallocz(sizeof(r2d_fpga_t));
+ s = g_malloc0(sizeof(r2d_fpga_t));
s->irl = irl;
- iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
- r2d_fpga_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x40, iomemtype);
+ memory_region_init_io(&s->iomem, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
}
typedef struct ResetData {
- CPUState *env;
+ SuperHCPU *cpu;
uint32_t vector;
} ResetData;
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
- CPUState *env = s->env;
+ CPUSH4State *env = &s->cpu->env;
- cpu_reset(env);
+ cpu_reset(CPU(s->cpu));
env->pc = s->vector;
}
-static struct __attribute__((__packed__))
+static struct QEMU_PACKED
{
int mount_root_rdonly;
int ramdisk_flags;
char kernel_cmdline[256];
} boot_params;
-static void r2d_init(ram_addr_t ram_size,
- const char *boot_device,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename, const char *cpu_model)
+static void r2d_init(QEMUMachineInitArgs *args)
{
- CPUState *env;
+ const char *cpu_model = args->cpu_model;
+ const char *kernel_filename = args->kernel_filename;
+ const char *kernel_cmdline = args->kernel_cmdline;
+ const char *initrd_filename = args->initrd_filename;
+ SuperHCPU *cpu;
+ CPUSH4State *env;
ResetData *reset_info;
struct SH7750State *s;
- ram_addr_t sdram_addr;
+ MemoryRegion *sdram = g_new(MemoryRegion, 1);
qemu_irq *irq;
DriveInfo *dinfo;
int i;
+ DeviceState *dev;
+ SysBusDevice *busdev;
+ MemoryRegion *address_space_mem = get_system_memory();
- if (!cpu_model)
+ if (cpu_model == NULL) {
cpu_model = "SH7751R";
+ }
- env = cpu_init(cpu_model);
- if (!env) {
+ cpu = cpu_sh4_init(cpu_model);
+ if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- reset_info = qemu_mallocz(sizeof(ResetData));
- reset_info->env = env;
+ env = &cpu->env;
+
+ reset_info = g_malloc0(sizeof(ResetData));
+ reset_info->cpu = cpu;
reset_info->vector = env->pc;
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate memory space */
- sdram_addr = qemu_ram_alloc(NULL, "r2d.sdram", SDRAM_SIZE);
- cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
+ memory_region_init_ram(sdram, "r2d.sdram", SDRAM_SIZE);
+ vmstate_register_ram_global(sdram);
+ memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
/* Register peripherals */
- s = sh7750_init(env);
- irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
- sysbus_create_varargs("sh_pci", 0x1e200000, irq[PCI_INTA], irq[PCI_INTB],
- irq[PCI_INTC], irq[PCI_INTD], NULL);
-
- sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
+ s = sh7750_init(env, address_space_mem);
+ irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
+
+ dev = qdev_create(NULL, "sh_pci");
+ busdev = sysbus_from_qdev(dev);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
+ sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
+ sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
+ sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
+ sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
+ sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
+
+ sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE,
+ irq[SM501], serial_hds[2]);
/* onboard CF (True IDE mode, Master only). */
dinfo = drive_get(IF_IDE, 0, 0);
- mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
+ mmio_ide_init(0x14001000, 0x1400080c, address_space_mem, irq[CF_IDE], 1,
dinfo, NULL);
/* onboard flash memory */
dinfo = drive_get(IF_PFLASH, 0, 0);
- pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE),
+ pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
dinfo ? dinfo->bdrv : NULL, (16 * 1024),
FLASH_SIZE >> 16,
1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
}
if (kernel_cmdline) {
+ /* I see no evidence that this .kernel_cmdline buffer requires
+ NUL-termination, so using strncpy should be ok. */
strncpy(boot_params.kernel_cmdline, kernel_cmdline,
sizeof(boot_params.kernel_cmdline));
}
projects / mirror_qemu.git / blobdiff