*/
#include "qemu/osdep.h"
-#include "qemu-common.h"
+#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "exec/cpu-defs.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/riscv/boot.h"
+#include "hw/riscv/boot_opensbi.h"
#include "elf.h"
#include "sysemu/device_tree.h"
#include "sysemu/qtest.h"
+#include "sysemu/kvm.h"
#include <libfdt.h>
-#if defined(TARGET_RISCV32)
-# define KERNEL_BOOT_ADDRESS 0x80400000
-#else
-# define KERNEL_BOOT_ADDRESS 0x80200000
-#endif
+bool riscv_is_32bit(RISCVHartArrayState *harts)
+{
+ return harts->harts[0].env.misa_mxl_max == MXL_RV32;
+}
-void riscv_find_and_load_firmware(MachineState *machine,
- const char *default_machine_firmware,
- hwaddr firmware_load_addr,
- symbol_fn_t sym_cb)
+/*
+ * Return the per-socket PLIC hart topology configuration string
+ * (caller must free with g_free())
+ */
+char *riscv_plic_hart_config_string(int hart_count)
+{
+ g_autofree const char **vals = g_new(const char *, hart_count + 1);
+ int i;
+
+ for (i = 0; i < hart_count; i++) {
+ CPUState *cs = qemu_get_cpu(i);
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (kvm_enabled()) {
+ vals[i] = "S";
+ } else if (riscv_has_ext(env, RVS)) {
+ vals[i] = "MS";
+ } else {
+ vals[i] = "M";
+ }
+ }
+ vals[i] = NULL;
+
+ /* g_strjoinv() obliges us to cast away const here */
+ return g_strjoinv(",", (char **)vals);
+}
+
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
+ target_ulong firmware_end_addr) {
+ if (riscv_is_32bit(harts)) {
+ return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
+ } else {
+ return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
+ }
+}
+
+target_ulong riscv_find_and_load_firmware(MachineState *machine,
+ const char *default_machine_firmware,
+ hwaddr firmware_load_addr,
+ symbol_fn_t sym_cb)
{
char *firmware_filename = NULL;
+ target_ulong firmware_end_addr = firmware_load_addr;
if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {
/*
if (firmware_filename) {
/* If not "none" load the firmware */
- riscv_load_firmware(firmware_filename, firmware_load_addr, sym_cb);
+ firmware_end_addr = riscv_load_firmware(firmware_filename,
+ firmware_load_addr, sym_cb);
g_free(firmware_filename);
}
+
+ return firmware_end_addr;
}
char *riscv_find_firmware(const char *firmware_filename)
hwaddr firmware_load_addr,
symbol_fn_t sym_cb)
{
- uint64_t firmware_entry, firmware_start, firmware_end;
+ uint64_t firmware_entry, firmware_size, firmware_end;
if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
- &firmware_entry, &firmware_start, &firmware_end, NULL,
+ &firmware_entry, NULL, &firmware_end, NULL,
0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
- return firmware_entry;
+ return firmware_end;
}
- if (load_image_targphys_as(firmware_filename, firmware_load_addr,
- ram_size, NULL) > 0) {
- return firmware_load_addr;
+ firmware_size = load_image_targphys_as(firmware_filename,
+ firmware_load_addr,
+ current_machine->ram_size, NULL);
+
+ if (firmware_size > 0) {
+ return firmware_load_addr + firmware_size;
}
error_report("could not load firmware '%s'", firmware_filename);
exit(1);
}
-target_ulong riscv_load_kernel(const char *kernel_filename, symbol_fn_t sym_cb)
+target_ulong riscv_load_kernel(const char *kernel_filename,
+ target_ulong kernel_start_addr,
+ symbol_fn_t sym_cb)
{
- uint64_t kernel_entry, kernel_high;
+ uint64_t kernel_load_base, kernel_entry;
+ /*
+ * NB: Use low address not ELF entry point to ensure that the fw_dynamic
+ * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL
+ * behaviour, as well as fw_dynamic with a raw binary, all of which jump to
+ * the (expected) load address load address. This allows kernels to have
+ * separate SBI and ELF entry points (used by FreeBSD, for example).
+ */
if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
- &kernel_entry, NULL, &kernel_high, NULL, 0,
+ NULL, &kernel_load_base, NULL, NULL, 0,
EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
- return kernel_entry;
+ return kernel_load_base;
}
if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
return kernel_entry;
}
- if (load_image_targphys_as(kernel_filename, KERNEL_BOOT_ADDRESS,
- ram_size, NULL) > 0) {
- return KERNEL_BOOT_ADDRESS;
+ if (load_image_targphys_as(kernel_filename, kernel_start_addr,
+ current_machine->ram_size, NULL) > 0) {
+ return kernel_start_addr;
}
error_report("could not load kernel '%s'", kernel_filename);
{
uint32_t temp, fdt_addr;
hwaddr dram_end = dram_base + mem_size;
- int fdtsize = fdt_totalsize(fdt);
+ int ret, fdtsize = fdt_totalsize(fdt);
if (fdtsize <= 0) {
error_report("invalid device-tree");
/*
* We should put fdt as far as possible to avoid kernel/initrd overwriting
* its content. But it should be addressable by 32 bit system as well.
- * Thus, put it at an aligned address that less than fdt size from end of
- * dram or 4GB whichever is lesser.
+ * Thus, put it at an 16MB aligned address that less than fdt size from the
+ * end of dram or 3GB whichever is lesser.
*/
- temp = MIN(dram_end, 4096 * MiB);
- fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+ temp = MIN(dram_end, 3072 * MiB);
+ fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
- fdt_pack(fdt);
+ ret = fdt_pack(fdt);
+ /* Should only fail if we've built a corrupted tree */
+ g_assert(ret == 0);
/* copy in the device tree */
qemu_fdt_dumpdtb(fdt, fdtsize);
return fdt_addr;
}
-void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
- hwaddr rom_size,
+void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
+ hwaddr rom_size, uint32_t reset_vec_size,
+ uint64_t kernel_entry)
+{
+ struct fw_dynamic_info dinfo;
+ size_t dinfo_len;
+
+ if (sizeof(dinfo.magic) == 4) {
+ dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
+ dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
+ dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
+ dinfo.next_addr = cpu_to_le32(kernel_entry);
+ } else {
+ dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
+ dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
+ dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
+ dinfo.next_addr = cpu_to_le64(kernel_entry);
+ }
+ dinfo.options = 0;
+ dinfo.boot_hart = 0;
+ dinfo_len = sizeof(dinfo);
+
+ /**
+ * copy the dynamic firmware info. This information is specific to
+ * OpenSBI but doesn't break any other firmware as long as they don't
+ * expect any certain value in "a2" register.
+ */
+ if (dinfo_len > (rom_size - reset_vec_size)) {
+ error_report("not enough space to store dynamic firmware info");
+ exit(1);
+ }
+
+ rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
+ rom_base + reset_vec_size,
+ &address_space_memory);
+}
+
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
+ hwaddr start_addr,
+ hwaddr rom_base, hwaddr rom_size,
+ uint64_t kernel_entry,
uint32_t fdt_load_addr, void *fdt)
{
int i;
+ uint32_t start_addr_hi32 = 0x00000000;
+ if (!riscv_is_32bit(harts)) {
+ start_addr_hi32 = start_addr >> 32;
+ }
/* reset vector */
uint32_t reset_vec[10] = {
- 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
+ 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
+ 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
-#if defined(TARGET_RISCV32)
- 0x0202a583, /* lw a1, 32(t0) */
- 0x0182a283, /* lw t0, 24(t0) */
-#elif defined(TARGET_RISCV64)
- 0x0202b583, /* ld a1, 32(t0) */
- 0x0182b283, /* ld t0, 24(t0) */
-#endif
+ 0,
+ 0,
0x00028067, /* jr t0 */
- 0x00000000,
start_addr, /* start: .dword */
- 0x00000000,
+ start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
- /* dtb: */
+ /* fw_dyn: */
};
+ if (riscv_is_32bit(harts)) {
+ reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
+ reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
+ } else {
+ reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */
+ reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
+ }
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
rom_base, &address_space_memory);
+ riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
+ kernel_entry);
return;
}
+
+void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
+{
+ CPUState *cs;
+
+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+ RISCVCPU *riscv_cpu = RISCV_CPU(cs);
+ riscv_cpu->env.kernel_addr = kernel_addr;
+ riscv_cpu->env.fdt_addr = fdt_addr;
+ }
+}