SiFiveESoCState *s = RISCV_E_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
- object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
+ object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
TYPE_SIFIVE_GPIO);
{
MachineState *ms = MACHINE(qdev_get_machine());
const struct MemmapEntry *memmap = sifive_e_memmap;
- Error *err = NULL;
-
SiFiveESoCState *s = RISCV_E_SOC(dev);
MemoryRegion *sys_mem = get_system_memory();
- object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
+ object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
/* GPIO */
- sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
- if (err) {
- error_propagate(errp, err);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}