*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/log.h"
+#include "qemu/module.h"
#include "qemu/error-report.h"
#include "hw/sysbus.h"
+#include "hw/pci/msi.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
#include "target/riscv/cpu.h"
+#include "sysemu/sysemu.h"
#include "hw/riscv/sifive_plic.h"
#define RISCV_DEBUG_PLIC 0
}
}
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq)
-{
- sifive_plic_set_pending(plic, irq, true);
- sifive_plic_update(plic);
-}
-
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq)
-{
- sifive_plic_set_pending(plic, irq, false);
- sifive_plic_update(plic);
-}
-
static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
{
int i, j;
+ uint32_t max_irq = 0;
+ uint32_t max_prio = plic->target_priority[addrid];
+
for (i = 0; i < plic->bitfield_words; i++) {
uint32_t pending_enabled_not_claimed =
(plic->pending[i] & ~plic->claimed[i]) &
int irq = (i << 5) + j;
uint32_t prio = plic->source_priority[irq];
int enabled = pending_enabled_not_claimed & (1 << j);
- if (enabled && prio > plic->target_priority[addrid]) {
- sifive_plic_set_pending(plic, irq, false);
- sifive_plic_set_claimed(plic, irq, true);
- return irq;
+ if (enabled && prio > max_prio) {
+ max_irq = irq;
+ max_prio = prio;
}
}
}
- return 0;
+
+ if (max_irq) {
+ sifive_plic_set_pending(plic, max_irq, false);
+ sifive_plic_set_claimed(plic, max_irq, true);
+ }
+ return max_irq;
}
static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
if (addr >= plic->priority_base && /* 4 bytes per source */
addr < plic->priority_base + (plic->num_sources << 2))
{
- uint32_t irq = (addr - plic->priority_base) >> 2;
+ uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
if (RISCV_DEBUG_PLIC) {
qemu_log("plic: read priority: irq=%d priority=%d\n",
irq, plic->source_priority[irq]);
plic->addr_config[addrid].hartid,
mode_to_char(plic->addr_config[addrid].mode),
value);
- sifive_plic_print_state(plic);
}
+ sifive_plic_update(plic);
return value;
}
}
err:
- error_report("plic: invalid register read: %08x", (uint32_t)addr);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
return 0;
}
if (addr >= plic->priority_base && /* 4 bytes per source */
addr < plic->priority_base + (plic->num_sources << 2))
{
- uint32_t irq = (addr - plic->priority_base) >> 2;
+ uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
plic->source_priority[irq] = value & 7;
if (RISCV_DEBUG_PLIC) {
qemu_log("plic: write priority: irq=%d priority=%d\n",
irq, plic->source_priority[irq]);
}
+ sifive_plic_update(plic);
return;
} else if (addr >= plic->pending_base && /* 1 bit per source */
addr < plic->pending_base + (plic->num_sources >> 3))
{
- error_report("plic: invalid pending write: %08x", (uint32_t)addr);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid pending write: 0x%" HWADDR_PRIx "",
+ __func__, addr);
return;
} else if (addr >= plic->enable_base && /* 1 bit per source */
addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
}
err:
- error_report("plic: invalid register write: %08x", (uint32_t)addr);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
}
static const MemoryRegionOps sifive_plic_ops = {
static void sifive_plic_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int smp_cpus = ms->smp.cpus;
SiFivePLICState *plic = SIFIVE_PLIC(dev);
+ int i;
memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
TYPE_SIFIVE_PLIC, plic->aperture_size);
plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
+
+ /* We can't allow the supervisor to control SEIP as this would allow the
+ * supervisor to clear a pending external interrupt which will result in
+ * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
+ * hardware controlled when a PLIC is attached.
+ */
+ for (i = 0; i < smp_cpus; i++) {
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
+ if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
+ error_report("SEIP already claimed");
+ exit(1);
+ }
+ }
+
+ msi_nonbroken = true;
}
static void sifive_plic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = sifive_plic_properties;
+ device_class_set_props(dc, sifive_plic_properties);
dc->realize = sifive_plic_realize;
}
uint32_t context_base, uint32_t context_stride,
uint32_t aperture_size)
{
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PLIC);
+ DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
assert(enable_stride == (enable_stride & -enable_stride));
assert(context_stride == (context_stride & -context_stride));
qdev_prop_set_string(dev, "hart-config", hart_config);
qdev_prop_set_uint32(dev, "context-base", context_base);
qdev_prop_set_uint32(dev, "context-stride", context_stride);
qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
projects / mirror_qemu.git / blobdiff