* segmentation offloading
* Removed slirp.h dependency
* Added rx/tx buffer reset when enabling rx/tx operation
+ *
+ * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
+ * when strictly needed (required for for
+ * Darwin)
+ * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
*/
+/* For crc32 */
+#include <zlib.h>
+
#include "hw.h"
#include "pci.h"
+#include "dma.h"
#include "qemu-timer.h"
#include "net.h"
+#include "loader.h"
+#include "sysemu.h"
+#include "iov.h"
/* debug RTL8139 card */
//#define DEBUG_RTL8139 1
/* debug RTL8139 card C+ mode only */
//#define DEBUG_RTL8139CP 1
-/* Calculate CRCs properly on Rx packets */
-#define RTL8139_CALCULATE_RXCRC 1
-
-/* Uncomment to enable on-board timer interrupts */
-//#define RTL8139_ONBOARD_TIMER 1
-
-#if defined(RTL8139_CALCULATE_RXCRC)
-/* For crc32 */
-#include <zlib.h>
-#endif
-
#define SET_MASKED(input, mask, curr) \
( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
#define MOD2(input, size) \
( ( input ) & ( size - 1 ) )
+#define ETHER_ADDR_LEN 6
+#define ETHER_TYPE_LEN 2
+#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
+#define ETH_P_IP 0x0800 /* Internet Protocol packet */
+#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
+#define ETH_MTU 1500
+
+#define VLAN_TCI_LEN 2
+#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
+
#if defined (DEBUG_RTL8139)
-# define DEBUG_PRINT(x) do { printf x ; } while (0)
+# define DPRINTF(fmt, ...) \
+ do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
#else
-# define DEBUG_PRINT(x)
+static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
+{
+ return 0;
+}
#endif
/* Symbolic offsets to registers. */
/* Clears all tally counters */
static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
-/* Writes tally counters to specified physical memory address */
-static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
-
-/* Loads values of tally counters from VM state file */
-static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
-
-/* Saves values of tally counters to VM state file */
-static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
-
typedef struct RTL8139State {
+ PCIDevice dev;
uint8_t phys[8]; /* mac address */
uint8_t mult[8]; /* multicast mask array */
uint16_t CpCmd;
uint8_t TxThresh;
- PCIDevice *pci_dev;
- VLANClientState *vc;
- uint8_t macaddr[6];
- int rtl8139_mmio_io_addr;
+ NICState *nic;
+ NICConf conf;
/* C ring mode */
uint32_t currTxDesc;
/* PCI interrupt timer */
QEMUTimer *timer;
+ int64_t TimerExpire;
+
+ MemoryRegion bar_io;
+ MemoryRegion bar_mem;
+ /* Support migration to/from old versions */
+ int rtl8139_mmio_io_addr_dummy;
} RTL8139State;
+/* Writes tally counters to memory via DMA */
+static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
+
+static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
+
static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
{
- DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
+ DPRINTF("eeprom command 0x%02x\n", command);
switch (command & Chip9346_op_mask)
{
eeprom->eedo = 0;
eeprom->tick = 0;
eeprom->mode = Chip9346_data_read;
- DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
- eeprom->address, eeprom->output));
+ DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
+ eeprom->address, eeprom->output);
}
break;
eeprom->input = 0;
eeprom->tick = 0;
eeprom->mode = Chip9346_none; /* Chip9346_data_write */
- DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
- eeprom->address));
+ DPRINTF("eeprom begin write to address 0x%02x\n",
+ eeprom->address);
}
break;
default:
switch (command & Chip9346_op_ext_mask)
{
case Chip9346_op_write_enable:
- DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
+ DPRINTF("eeprom write enabled\n");
break;
case Chip9346_op_write_all:
- DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
+ DPRINTF("eeprom begin write all\n");
break;
case Chip9346_op_write_disable:
- DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
+ DPRINTF("eeprom write disabled\n");
break;
}
break;
++ eeprom->tick;
- DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
+ DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
+ eeprom->eedo);
switch (eeprom->mode)
{
eeprom->mode = Chip9346_read_command;
eeprom->tick = 0;
eeprom->input = 0;
- DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
+ DPRINTF("eeprom: +++ synchronized, begin command read\n");
}
break;
eeprom->input = 0;
eeprom->tick = 0;
- DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
+ DPRINTF("eeprom: +++ end of read, awaiting next command\n");
#else
// original behaviour
++eeprom->address;
eeprom->output = eeprom->contents[eeprom->address];
eeprom->tick = 0;
- DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
- eeprom->address, eeprom->output));
+ DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
+ eeprom->address, eeprom->output);
#endif
}
break;
eeprom->input = (eeprom->input << 1) | (bit & 1);
if (eeprom->tick == 16)
{
- DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
- eeprom->address, eeprom->input));
+ DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
+ eeprom->address, eeprom->input);
eeprom->contents[eeprom->address] = eeprom->input;
eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
{
eeprom->contents[i] = eeprom->input;
}
- DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
- eeprom->input));
+ DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
eeprom->mode = Chip9346_enter_command_mode;
eeprom->tick = 0;
eeprom->eesk = eesk;
eeprom->eedi = eedi;
- DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
- eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
+ DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
+ eeprom->eesk, eeprom->eedi, eeprom->eedo);
if (!old_eecs && eecs)
{
eeprom->output = 0;
eeprom->mode = Chip9346_enter_command_mode;
- DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
+ DPRINTF("=== eeprom: begin access, enter command mode\n");
}
if (!eecs)
{
- DEBUG_PRINT(("=== eeprom: end access\n"));
+ DPRINTF("=== eeprom: end access\n");
return;
}
int isr;
isr = (s->IntrStatus & s->IntrMask) & 0xffff;
- DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
- isr ? 1 : 0, s->IntrStatus, s->IntrMask));
+ DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
+ s->IntrMask);
- qemu_set_irq(s->pci_dev->irq[0], (isr != 0));
+ qemu_set_irq(s->dev.irq[0], (isr != 0));
}
#define POLYNOMIAL 0x04c11db6
/* write packet data */
if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
{
- DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
+ DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
if (size > wrapped)
{
- cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
- buf, size-wrapped );
+ pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
+ buf, size-wrapped);
}
/* reset buffer pointer */
s->RxBufAddr = 0;
- cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
- buf + (size-wrapped), wrapped );
+ pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
+ buf + (size-wrapped), wrapped);
s->RxBufAddr = wrapped;
}
/* non-wrapping path or overwrapping enabled */
- cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
+ pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size);
s->RxBufAddr += size;
}
#define MIN_BUF_SIZE 60
-static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
+static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
{
#if TARGET_PHYS_ADDR_BITS > 32
return low | ((target_phys_addr_t)high << 32);
#endif
}
-static int rtl8139_can_receive(VLANClientState *vc)
+static int rtl8139_can_receive(VLANClientState *nc)
{
- RTL8139State *s = vc->opaque;
+ RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
int avail;
/* Receive (drop) packets if card is disabled. */
}
}
-static ssize_t rtl8139_do_receive(VLANClientState *vc, const uint8_t *buf, size_t size_, int do_interrupt)
+static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
{
- RTL8139State *s = vc->opaque;
+ RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
+ /* size is the length of the buffer passed to the driver */
int size = size_;
+ const uint8_t *dot1q_buf = NULL;
uint32_t packet_header = 0;
- uint8_t buf1[60];
+ uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
static const uint8_t broadcast_macaddr[6] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
- DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
+ DPRINTF(">>> received len=%d\n", size);
/* test if board clock is stopped */
if (!s->clock_enabled)
{
- DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
+ DPRINTF("stopped ==========================\n");
return -1;
}
if (!rtl8139_receiver_enabled(s))
{
- DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
+ DPRINTF("receiver disabled ================\n");
return -1;
}
/* XXX: check this */
if (s->RxConfig & AcceptAllPhys) {
/* promiscuous: receive all */
- DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
+ DPRINTF(">>> packet received in promiscuous mode\n");
} else {
if (!memcmp(buf, broadcast_macaddr, 6)) {
/* broadcast address */
if (!(s->RxConfig & AcceptBroadcast))
{
- DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
+ DPRINTF(">>> broadcast packet rejected\n");
/* update tally counter */
++s->tally_counters.RxERR;
packet_header |= RxBroadcast;
- DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
+ DPRINTF(">>> broadcast packet received\n");
/* update tally counter */
++s->tally_counters.RxOkBrd;
/* multicast */
if (!(s->RxConfig & AcceptMulticast))
{
- DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
+ DPRINTF(">>> multicast packet rejected\n");
/* update tally counter */
++s->tally_counters.RxERR;
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
{
- DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
+ DPRINTF(">>> multicast address mismatch\n");
/* update tally counter */
++s->tally_counters.RxERR;
packet_header |= RxMulticast;
- DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
+ DPRINTF(">>> multicast packet received\n");
/* update tally counter */
++s->tally_counters.RxOkMul;
/* match */
if (!(s->RxConfig & AcceptMyPhys))
{
- DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
+ DPRINTF(">>> rejecting physical address matching packet\n");
/* update tally counter */
++s->tally_counters.RxERR;
packet_header |= RxPhysical;
- DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
+ DPRINTF(">>> physical address matching packet received\n");
/* update tally counter */
++s->tally_counters.RxOkPhy;
} else {
- DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
+ DPRINTF(">>> unknown packet\n");
/* update tally counter */
++s->tally_counters.RxERR;
}
}
- /* if too small buffer, then expand it */
- if (size < MIN_BUF_SIZE) {
+ /* if too small buffer, then expand it
+ * Include some tailroom in case a vlan tag is later removed. */
+ if (size < MIN_BUF_SIZE + VLAN_HLEN) {
memcpy(buf1, buf, size);
- memset(buf1 + size, 0, MIN_BUF_SIZE - size);
+ memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
buf = buf1;
- size = MIN_BUF_SIZE;
+ if (size < MIN_BUF_SIZE) {
+ size = MIN_BUF_SIZE;
+ }
}
if (rtl8139_cp_receiver_enabled(s))
{
- DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
+ DPRINTF("in C+ Rx mode ================\n");
/* begin C+ receiver mode */
/* w3 high 32bit of Rx buffer ptr */
int descriptor = s->currCPlusRxDesc;
- target_phys_addr_t cplus_rx_ring_desc;
+ dma_addr_t cplus_rx_ring_desc;
cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
cplus_rx_ring_desc += 16 * descriptor;
- DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
- descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
+ DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
+ "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
+ s->RxRingAddrLO, cplus_rx_ring_desc);
uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
- cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
+ pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4);
rxdw0 = le32_to_cpu(val);
- cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
+ pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4);
rxdw1 = le32_to_cpu(val);
- cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
+ pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4);
rxbufLO = le32_to_cpu(val);
- cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
+ pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4);
rxbufHI = le32_to_cpu(val);
- DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
- descriptor,
- rxdw0, rxdw1, rxbufLO, rxbufHI));
+ DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
+ descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
if (!(rxdw0 & CP_RX_OWN))
{
- DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
+ DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
+ descriptor);
s->IntrStatus |= RxOverflow;
++s->RxMissed;
uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
+ /* write VLAN info to descriptor variables. */
+ if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
+ &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
+ dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
+ size -= VLAN_HLEN;
+ /* if too small buffer, use the tailroom added duing expansion */
+ if (size < MIN_BUF_SIZE) {
+ size = MIN_BUF_SIZE;
+ }
+
+ rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
+ /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
+ rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
+ &dot1q_buf[ETHER_TYPE_LEN]);
+
+ DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
+ be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
+ } else {
+ /* reset VLAN tag flag */
+ rxdw1 &= ~CP_RX_TAVA;
+ }
+
/* TODO: scatter the packet over available receive ring descriptors space */
if (size+4 > rx_space)
{
- DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
- descriptor, rx_space, size));
+ DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
+ descriptor, rx_space, size);
s->IntrStatus |= RxOverflow;
++s->RxMissed;
return size_;
}
- target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
+ dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
/* receive/copy to target memory */
- cpu_physical_memory_write( rx_addr, buf, size );
+ if (dot1q_buf) {
+ pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
+ pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,
+ buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
+ size - 2 * ETHER_ADDR_LEN);
+ } else {
+ pci_dma_write(&s->dev, rx_addr, buf, size);
+ }
if (s->CpCmd & CPlusRxChkSum)
{
}
/* write checksum */
-#if defined (RTL8139_CALCULATE_RXCRC)
- val = cpu_to_le32(crc32(0, buf, size));
-#else
- val = 0;
-#endif
- cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
+ val = cpu_to_le32(crc32(0, buf, size_));
+ pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4);
/* first segment of received packet flag */
#define CP_RX_STATUS_FS (1<<29)
rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
rxdw0 |= (size+4);
- /* reset VLAN tag flag */
- rxdw1 &= ~CP_RX_TAVA;
-
/* update ring data */
val = cpu_to_le32(rxdw0);
- cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
+ pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);
val = cpu_to_le32(rxdw1);
- cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
+ pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
/* update tally counter */
++s->tally_counters.RxOk;
++s->currCPlusRxDesc;
}
- DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
+ DPRINTF("done C+ Rx mode ----------------\n");
}
else
{
- DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
+ DPRINTF("in ring Rx mode ================\n");
/* begin ring receiver mode */
int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
if (avail != 0 && size + 8 >= avail)
{
- DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
- s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
+ DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
+ "read 0x%04x === available 0x%04x need 0x%04x\n",
+ s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
s->IntrStatus |= RxOverflow;
++s->RxMissed;
rtl8139_write_buffer(s, buf, size);
/* write checksum */
-#if defined (RTL8139_CALCULATE_RXCRC)
val = cpu_to_le32(crc32(0, buf, size));
-#else
- val = 0;
-#endif
-
rtl8139_write_buffer(s, (uint8_t *)&val, 4);
/* correct buffer write pointer */
/* now we can signal we have received something */
- DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
- s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
+ DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
+ s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
}
s->IntrStatus |= RxOK;
return size_;
}
-static ssize_t rtl8139_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
+static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
{
- return rtl8139_do_receive(vc, buf, size, 1);
+ return rtl8139_do_receive(nc, buf, size, 1);
}
static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
s->RxBufAddr = 0;
}
-static void rtl8139_reset(void *opaque)
+static void rtl8139_reset(DeviceState *d)
{
- RTL8139State *s = opaque;
+ RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
int i;
/* restore MAC address */
- memcpy(s->phys, s->macaddr, 6);
+ memcpy(s->phys, s->conf.macaddr.a, 6);
/* reset interrupt mask */
s->IntrStatus = 0;
rtl8139_update_irq(s);
- /* prepare eeprom */
- s->eeprom.contents[0] = 0x8129;
-#if 1
- // PCI vendor and device ID should be mirrored here
- s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
- s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
-#endif
-
- s->eeprom.contents[7] = s->macaddr[0] | s->macaddr[1] << 8;
- s->eeprom.contents[8] = s->macaddr[2] | s->macaddr[3] << 8;
- s->eeprom.contents[9] = s->macaddr[4] | s->macaddr[5] << 8;
-
/* mark all status registers as owned by host */
for (i = 0; i < 4; ++i)
{
counters->TxUndrn = 0;
}
-static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
+static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
{
+ RTL8139TallyCounters *tally_counters = &s->tally_counters;
uint16_t val16;
uint32_t val32;
uint64_t val64;
val64 = cpu_to_le64(tally_counters->TxOk);
- cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
+ pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8);
val64 = cpu_to_le64(tally_counters->RxOk);
- cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
+ pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8);
val64 = cpu_to_le64(tally_counters->TxERR);
- cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
+ pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8);
val32 = cpu_to_le32(tally_counters->RxERR);
- cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
+ pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4);
val16 = cpu_to_le16(tally_counters->MissPkt);
- cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
+ pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2);
val16 = cpu_to_le16(tally_counters->FAE);
- cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
+ pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2);
val32 = cpu_to_le32(tally_counters->Tx1Col);
- cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
+ pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4);
val32 = cpu_to_le32(tally_counters->TxMCol);
- cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
+ pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4);
val64 = cpu_to_le64(tally_counters->RxOkPhy);
- cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
+ pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8);
val64 = cpu_to_le64(tally_counters->RxOkBrd);
- cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
+ pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8);
val32 = cpu_to_le32(tally_counters->RxOkMul);
- cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
+ pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4);
val16 = cpu_to_le16(tally_counters->TxAbt);
- cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
+ pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2);
val16 = cpu_to_le16(tally_counters->TxUndrn);
- cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
+ pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2);
}
/* Loads values of tally counters from VM state file */
-static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
-{
- qemu_get_be64s(f, &tally_counters->TxOk);
- qemu_get_be64s(f, &tally_counters->RxOk);
- qemu_get_be64s(f, &tally_counters->TxERR);
- qemu_get_be32s(f, &tally_counters->RxERR);
- qemu_get_be16s(f, &tally_counters->MissPkt);
- qemu_get_be16s(f, &tally_counters->FAE);
- qemu_get_be32s(f, &tally_counters->Tx1Col);
- qemu_get_be32s(f, &tally_counters->TxMCol);
- qemu_get_be64s(f, &tally_counters->RxOkPhy);
- qemu_get_be64s(f, &tally_counters->RxOkBrd);
- qemu_get_be32s(f, &tally_counters->RxOkMul);
- qemu_get_be16s(f, &tally_counters->TxAbt);
- qemu_get_be16s(f, &tally_counters->TxUndrn);
-}
-
-/* Saves values of tally counters to VM state file */
-static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
-{
- qemu_put_be64s(f, &tally_counters->TxOk);
- qemu_put_be64s(f, &tally_counters->RxOk);
- qemu_put_be64s(f, &tally_counters->TxERR);
- qemu_put_be32s(f, &tally_counters->RxERR);
- qemu_put_be16s(f, &tally_counters->MissPkt);
- qemu_put_be16s(f, &tally_counters->FAE);
- qemu_put_be32s(f, &tally_counters->Tx1Col);
- qemu_put_be32s(f, &tally_counters->TxMCol);
- qemu_put_be64s(f, &tally_counters->RxOkPhy);
- qemu_put_be64s(f, &tally_counters->RxOkBrd);
- qemu_put_be32s(f, &tally_counters->RxOkMul);
- qemu_put_be16s(f, &tally_counters->TxAbt);
- qemu_put_be16s(f, &tally_counters->TxUndrn);
-}
+
+static const VMStateDescription vmstate_tally_counters = {
+ .name = "tally_counters",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
+ VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
+ VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
+ VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
+ VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
+ VMSTATE_UINT16(FAE, RTL8139TallyCounters),
+ VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
+ VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
+ VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
+ VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
+ VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
+ VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
+ VMSTATE_END_OF_LIST()
+ }
+};
static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
+ DPRINTF("ChipCmd write val=0x%08x\n", val);
if (val & CmdReset)
{
- DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
- rtl8139_reset(s);
+ DPRINTF("ChipCmd reset\n");
+ rtl8139_reset(&s->dev.qdev);
}
if (val & CmdRxEnb)
{
- DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
+ DPRINTF("ChipCmd enable receiver\n");
s->currCPlusRxDesc = 0;
}
if (val & CmdTxEnb)
{
- DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
+ DPRINTF("ChipCmd enable transmitter\n");
s->currCPlusTxDesc = 0;
}
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xe3, s->bChipCmdState);
/* Deassert reset pin before next read */
if (unread != 0)
{
- DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
+ DPRINTF("receiver buffer data available 0x%04x\n", unread);
return 0;
}
- DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
+ DPRINTF("receiver buffer is empty\n");
return 1;
}
if (rtl8139_RxBufferEmpty(s))
ret |= RxBufEmpty;
- DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
+ DPRINTF("ChipCmd read val=0x%04x\n", ret);
return ret;
}
{
val &= 0xffff;
- DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
+ DPRINTF("C+ command register write(w) val=0x%04x\n", val);
s->cplus_enabled = 1;
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xff84, s->CpCmd);
s->CpCmd = val;
{
uint32_t ret = s->CpCmd;
- DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
+ DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
return ret;
}
static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
+ DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
}
static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
{
uint32_t ret = 0;
- DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
+ DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
return ret;
}
-static int rtl8139_config_writeable(RTL8139State *s)
+static int rtl8139_config_writable(RTL8139State *s)
{
if (s->Cfg9346 & Cfg9346_Unlock)
{
return 1;
}
- DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
+ DPRINTF("Configuration registers are write-protected\n");
return 0;
}
{
val &= 0xffff;
- DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
+ DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
uint32_t mask = 0x4cff;
- if (1 || !rtl8139_config_writeable(s))
+ if (1 || !rtl8139_config_writable(s))
{
/* Speed setting and autonegotiation enable bits are read-only */
mask |= 0x3000;
{
uint32_t ret = s->BasicModeCtrl;
- DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
+ DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
return ret;
}
{
val &= 0xffff;
- DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
+ DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
s->BasicModeStatus = val;
{
uint32_t ret = s->BasicModeStatus;
- DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
+ DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
+ DPRINTF("Cfg9346 write val=0x%02x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x31, s->Cfg9346);
uint32_t opmode = val & 0xc0;
} else if (opmode == 0x40) {
/* Reset. */
val = 0;
- rtl8139_reset(s);
+ rtl8139_reset(&s->dev.qdev);
}
s->Cfg9346 = val;
}
}
- DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
+ DPRINTF("Cfg9346 read val=0x%02x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
+ DPRINTF("Config0 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xf8, s->Config0);
s->Config0 = val;
{
uint32_t ret = s->Config0;
- DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
+ DPRINTF("Config0 read val=0x%02x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
+ DPRINTF("Config1 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xC, s->Config1);
s->Config1 = val;
{
uint32_t ret = s->Config1;
- DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
+ DPRINTF("Config1 read val=0x%02x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
+ DPRINTF("Config3 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x8F, s->Config3);
s->Config3 = val;
{
uint32_t ret = s->Config3;
- DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
+ DPRINTF("Config3 read val=0x%02x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
+ DPRINTF("Config4 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x0a, s->Config4);
s->Config4 = val;
{
uint32_t ret = s->Config4;
- DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
+ DPRINTF("Config4 read val=0x%02x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
+ DPRINTF("Config5 write val=0x%02x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x80, s->Config5);
s->Config5 = val;
{
uint32_t ret = s->Config5;
- DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
+ DPRINTF("Config5 read val=0x%02x\n", ret);
return ret;
}
{
if (!rtl8139_transmitter_enabled(s))
{
- DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
+ DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
return;
}
- DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
+ DPRINTF("TxConfig write val=0x%08x\n", val);
val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
+ DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
uint32_t tc = s->TxConfig;
tc &= 0xFFFFFF00;
{
uint32_t ret = s->TxConfig;
- DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
+ DPRINTF("TxConfig read val=0x%04x\n", ret);
return ret;
}
static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
+ DPRINTF("RxConfig write val=0x%08x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
s->RxConfig = val;
/* reset buffer size and read/write pointers */
rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
- DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
+ DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
}
static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
{
uint32_t ret = s->RxConfig;
- DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
+ DPRINTF("RxConfig read val=0x%08x\n", ret);
return ret;
}
-static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
+static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
+ int do_interrupt, const uint8_t *dot1q_buf)
{
+ struct iovec *iov = NULL;
+
if (!size)
{
- DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
+ DPRINTF("+++ empty ethernet frame\n");
return;
}
+ if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
+ iov = (struct iovec[3]) {
+ { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
+ { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
+ { .iov_base = buf + ETHER_ADDR_LEN * 2,
+ .iov_len = size - ETHER_ADDR_LEN * 2 },
+ };
+ }
+
if (TxLoopBack == (s->TxConfig & TxLoopBack))
{
- DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
- rtl8139_do_receive(s->vc, buf, size, do_interrupt);
+ size_t buf2_size;
+ uint8_t *buf2;
+
+ if (iov) {
+ buf2_size = iov_size(iov, 3);
+ buf2 = g_malloc(buf2_size);
+ iov_to_buf(iov, 3, buf2, 0, buf2_size);
+ buf = buf2;
+ }
+
+ DPRINTF("+++ transmit loopback mode\n");
+ rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
+
+ if (iov) {
+ g_free(buf2);
+ }
}
else
{
- qemu_send_packet(s->vc, buf, size);
+ if (iov) {
+ qemu_sendv_packet(&s->nic->nc, iov, 3);
+ } else {
+ qemu_send_packet(&s->nic->nc, buf, size);
+ }
}
}
{
if (!rtl8139_transmitter_enabled(s))
{
- DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
- descriptor));
+ DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
+ "disabled\n", descriptor);
return 0;
}
if (s->TxStatus[descriptor] & TxHostOwns)
{
- DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
- descriptor, s->TxStatus[descriptor]));
+ DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
+ "(%08x)\n", descriptor, s->TxStatus[descriptor]);
return 0;
}
- DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
+ DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
int txsize = s->TxStatus[descriptor] & 0x1fff;
uint8_t txbuffer[0x2000];
- DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
- txsize, s->TxAddr[descriptor]));
+ DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
+ txsize, s->TxAddr[descriptor]);
- cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
+ pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize);
/* Mark descriptor as transferred */
s->TxStatus[descriptor] |= TxHostOwns;
s->TxStatus[descriptor] |= TxStatOK;
- rtl8139_transfer_frame(s, txbuffer, txsize, 0);
+ rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
- DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
+ DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
+ descriptor);
/* update interrupt */
s->IntrStatus |= TxOK;
{
if (!rtl8139_transmitter_enabled(s))
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
+ DPRINTF("+++ C+ mode: transmitter disabled\n");
return 0;
}
if (!rtl8139_cp_transmitter_enabled(s))
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
+ DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
return 0 ;
}
int descriptor = s->currCPlusTxDesc;
- target_phys_addr_t cplus_tx_ring_desc =
- rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
+ dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
/* Normal priority ring */
cplus_tx_ring_desc += 16 * descriptor;
- DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
- descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
+ DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
+ "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
+ s->TxAddr[0], cplus_tx_ring_desc);
uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
- cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
+ pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
txdw0 = le32_to_cpu(val);
- cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
+ pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
txdw1 = le32_to_cpu(val);
- cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
+ pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
txbufLO = le32_to_cpu(val);
- cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
+ pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
txbufHI = le32_to_cpu(val);
- DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
- descriptor,
- txdw0, txdw1, txbufLO, txbufHI));
+ DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
+ txdw0, txdw1, txbufLO, txbufHI);
/* w0 ownership flag */
#define CP_TX_OWN (1<<31)
/* w0 bits 0...15 : buffer size */
#define CP_TX_BUFFER_SIZE (1<<16)
#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
-/* w1 tag available flag */
-#define CP_RX_TAGC (1<<17)
-/* w1 bits 0...15 : VLAN tag */
+/* w1 add tag flag */
+#define CP_TX_TAGC (1<<17)
+/* w1 bits 0...15 : VLAN tag (big endian) */
#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
/* w2 low 32bit of Rx buffer ptr */
/* w3 high 32bit of Rx buffer ptr */
if (!(txdw0 & CP_TX_OWN))
{
- DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
+ DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
return 0 ;
}
- DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
+ DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
if (txdw0 & CP_TX_FS)
{
- DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
+ DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
+ "descriptor\n", descriptor);
/* reset internal buffer offset */
s->cplus_txbuffer_offset = 0;
}
int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
- target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
+ dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
/* make sure we have enough space to assemble the packet */
if (!s->cplus_txbuffer)
{
s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
- s->cplus_txbuffer = malloc(s->cplus_txbuffer_len);
+ s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
s->cplus_txbuffer_offset = 0;
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
+ DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
+ s->cplus_txbuffer_len);
}
while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
{
s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
- s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
+ s->cplus_txbuffer = g_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
+ DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
+ s->cplus_txbuffer_len);
}
if (!s->cplus_txbuffer)
{
/* out of memory */
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
+ DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
+ s->cplus_txbuffer_len);
/* update tally counter */
++s->tally_counters.TxERR;
/* append more data to the packet */
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
- txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
+ DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
+ DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
+ s->cplus_txbuffer_offset);
- cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
+ pci_dma_read(&s->dev, tx_addr,
+ s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
s->cplus_txbuffer_offset += txsize;
/* seek to next Rx descriptor */
/* update ring data */
val = cpu_to_le32(txdw0);
- cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
-// val = cpu_to_le32(txdw1);
-// cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
+ pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
/* Now decide if descriptor being processed is holding the last segment of packet */
if (txdw0 & CP_TX_LS)
{
- DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
+ uint8_t dot1q_buffer_space[VLAN_HLEN];
+ uint16_t *dot1q_buffer;
+
+ DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
+ descriptor);
/* can transfer fully assembled packet */
int saved_size = s->cplus_txbuffer_offset;
int saved_buffer_len = s->cplus_txbuffer_len;
+ /* create vlan tag */
+ if (txdw1 & CP_TX_TAGC) {
+ /* the vlan tag is in BE byte order in the descriptor
+ * BE + le_to_cpu() + ~swap()~ = cpu */
+ DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
+ bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
+
+ dot1q_buffer = (uint16_t *) dot1q_buffer_space;
+ dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
+ /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
+ dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
+ } else {
+ dot1q_buffer = NULL;
+ }
+
/* reset the card space to protect from recursive call */
s->cplus_txbuffer = NULL;
s->cplus_txbuffer_offset = 0;
if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
-
- #define ETH_P_IP 0x0800 /* Internet Protocol packet */
- #define ETH_HLEN 14
- #define ETH_MTU 1500
+ DPRINTF("+++ C+ mode offloaded task checksum\n");
/* ip packet header */
ip_header *ip = NULL;
int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
if (proto == ETH_P_IP)
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
+ DPRINTF("+++ C+ mode has IP packet\n");
/* not aligned */
eth_payload_data = saved_buffer + ETH_HLEN;
ip = (ip_header*)eth_payload_data;
if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
- DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
+ DPRINTF("+++ C+ mode packet has bad IP version %d "
+ "expected %d\n", IP_HEADER_VERSION(ip),
+ IP_HEADER_VERSION_4);
ip = NULL;
} else {
hlen = IP_HEADER_LENGTH(ip);
{
if (txdw0 & CP_TX_IPCS)
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
+ DPRINTF("+++ C+ mode need IP checksum\n");
if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
/* bad packet header len */
{
ip->ip_sum = 0;
ip->ip_sum = ip_checksum(ip, hlen);
- DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
+ DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
+ hlen, ip->ip_sum);
}
}
if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
{
-#if defined (DEBUG_RTL8139)
int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
-#endif
- DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
- ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
+
+ DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
+ "frame data %d specified MSS=%d\n", ETH_MTU,
+ ip_data_len, saved_size - ETH_HLEN, large_send_mss);
int tcp_send_offset = 0;
int send_count = 0;
int tcp_data_len = ip_data_len - tcp_hlen;
int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
- ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
+ DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
+ "data len %d TCP chunk size %d\n", ip_data_len,
+ tcp_hlen, tcp_data_len, tcp_chunk_size);
/* note the cycle below overwrites IP header data,
but restores it from saved_ip_header before sending packet */
chunk_size = tcp_data_len - tcp_send_offset;
}
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
+ DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
+ be32_to_cpu(p_tcp_hdr->th_seq));
/* add 4 TCP pseudoheader fields */
/* copy IP source and destination fields */
memcpy(data_to_checksum, saved_ip_header + 12, 8);
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
+ DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
+ "packet with %d bytes data\n", tcp_hlen +
+ chunk_size);
if (tcp_send_offset)
{
p_tcp_hdr->th_sum = 0;
int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
+ DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
+ tcp_checksum);
p_tcp_hdr->th_sum = tcp_checksum;
ip->ip_sum = 0;
ip->ip_sum = ip_checksum(eth_payload_data, hlen);
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
+ DPRINTF("+++ C+ mode TSO IP header len=%d "
+ "checksum=%04x\n", hlen, ip->ip_sum);
int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
- rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
+ DPRINTF("+++ C+ mode TSO transferring packet size "
+ "%d\n", tso_send_size);
+ rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
+ 0, (uint8_t *) dot1q_buffer);
/* add transferred count to TCP sequence number */
p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
}
else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
+ DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
/* maximum IP header length is 60 bytes */
uint8_t saved_ip_header[60];
if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
+ DPRINTF("+++ C+ mode calculating TCP checksum for "
+ "packet with %d bytes data\n", ip_data_len);
ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
p_tcpip_hdr->zeros = 0;
p_tcp_hdr->th_sum = 0;
int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
- DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
+ DPRINTF("+++ C+ mode TCP checksum %04x\n",
+ tcp_checksum);
p_tcp_hdr->th_sum = tcp_checksum;
}
else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
+ DPRINTF("+++ C+ mode calculating UDP checksum for "
+ "packet with %d bytes data\n", ip_data_len);
ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
p_udpip_hdr->zeros = 0;
p_udp_hdr->uh_sum = 0;
int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
- DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
+ DPRINTF("+++ C+ mode UDP checksum %04x\n",
+ udp_checksum);
p_udp_hdr->uh_sum = udp_checksum;
}
/* update tally counter */
++s->tally_counters.TxOk;
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
+ DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
- rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
+ rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
+ (uint8_t *) dot1q_buffer);
/* restore card space if there was no recursion and reset offset */
if (!s->cplus_txbuffer)
}
else
{
- free(saved_buffer);
+ g_free(saved_buffer);
}
}
else
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
+ DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
}
return 1;
/* Mark transfer completed */
if (!txcount)
{
- DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
- s->currCPlusTxDesc));
+ DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
+ s->currCPlusTxDesc);
}
else
{
/* Mark transfer completed */
if (!txcount)
{
- DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
+ DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
+ s->currTxDesc);
}
}
if (s->cplus_enabled)
{
- DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
+ DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
+ "descriptor=%d\n", txRegOffset, val, descriptor);
/* handle Dump Tally Counters command */
s->TxStatus[descriptor] = val;
target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
/* dump tally counters to specified memory location */
- RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
+ RTL8139TallyCounters_dma_write(s, tc_addr);
/* mark dump completed */
s->TxStatus[0] &= ~0x8;
return;
}
- DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
+ DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
+ txRegOffset, val, descriptor);
/* mask only reserved bits */
val &= ~0xff00c000; /* these bits are reset on write */
{
uint32_t ret = s->TxStatus[txRegOffset/4];
- DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
+ DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
return ret;
}
|((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
- DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
+ DPRINTF("TSAD read val=0x%04x\n", ret);
return ret;
}
{
uint16_t ret = s->CSCR;
- DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
+ DPRINTF("CSCR read val=0x%04x\n", ret);
return ret;
}
static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
+ DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
s->TxAddr[txAddrOffset/4] = val;
}
{
uint32_t ret = s->TxAddr[txAddrOffset/4];
- DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
+ DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
return ret;
}
static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
+ DPRINTF("RxBufPtr write val=0x%04x\n", val);
/* this value is off by 16 */
s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
- DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
- s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
+ DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
+ s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
}
static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
/* this value is off by 16 */
uint32_t ret = s->RxBufPtr - 0x10;
- DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
+ DPRINTF("RxBufPtr read val=0x%04x\n", ret);
return ret;
}
/* this value is NOT off by 16 */
uint32_t ret = s->RxBufAddr;
- DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
+ DPRINTF("RxBufAddr read val=0x%04x\n", ret);
return ret;
}
static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
+ DPRINTF("RxBuf write val=0x%08x\n", val);
s->RxBuf = val;
{
uint32_t ret = s->RxBuf;
- DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
+ DPRINTF("RxBuf read val=0x%08x\n", ret);
return ret;
}
static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
+ DPRINTF("IntrMask write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x1e00, s->IntrMask);
s->IntrMask = val;
+ rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
rtl8139_update_irq(s);
+
}
static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
{
uint32_t ret = s->IntrMask;
- DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
+ DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
return ret;
}
static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
+ DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
#if 0
#else
uint16_t newStatus = s->IntrStatus & ~val;
- /* mask unwriteable bits */
+ /* mask unwritable bits */
newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
/* writing 1 to interrupt status register bit clears it */
rtl8139_update_irq(s);
s->IntrStatus = newStatus;
+ /*
+ * Computing if we miss an interrupt here is not that correct but
+ * considered that we should have had already an interrupt
+ * and probably emulated is slower is better to assume this resetting was
+ * done before testing on previous rtl8139_update_irq lead to IRQ losing
+ */
+ rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
rtl8139_update_irq(s);
+
#endif
}
static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
{
+ rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
+
uint32_t ret = s->IntrStatus;
- DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
+ DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
#if 0
static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
+ DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xf000, s->MultiIntr);
s->MultiIntr = val;
{
uint32_t ret = s->MultiIntr;
- DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
+ DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
return ret;
}
{
RTL8139State *s = opaque;
- addr &= 0xff;
-
switch (addr)
{
case MAC0 ... MAC0+5:
break;
case MediaStatus:
/* ignore */
- DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
+ DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
+ val);
break;
case HltClk:
- DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
+ DPRINTF("HltClk write val=0x%08x\n", val);
if (val == 'R')
{
s->clock_enabled = 1;
break;
case TxThresh:
- DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
+ DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
s->TxThresh = val;
break;
case TxPoll:
- DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
+ DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
if (val & (1 << 7))
{
- DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
+ DPRINTF("C+ TxPoll high priority transmission (not "
+ "implemented)\n");
//rtl8139_cplus_transmit(s);
}
if (val & (1 << 6))
{
- DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
+ DPRINTF("C+ TxPoll normal priority transmission\n");
rtl8139_cplus_transmit(s);
}
break;
default:
- DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
+ DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
+ val);
break;
}
}
{
RTL8139State *s = opaque;
- addr &= 0xfe;
-
switch (addr)
{
case IntrMask:
rtl8139_BasicModeStatus_write(s, val);
break;
case NWayAdvert:
- DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
+ DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
s->NWayAdvert = val;
break;
case NWayLPAR:
- DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
+ DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
break;
case NWayExpansion:
- DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
+ DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
s->NWayExpansion = val;
break;
break;
default:
- DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
+ DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
+ addr, val);
rtl8139_io_writeb(opaque, addr, val & 0xff);
rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}
}
+static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
+{
+ int64_t pci_time, next_time;
+ uint32_t low_pci;
+
+ DPRINTF("entered rtl8139_set_next_tctr_time\n");
+
+ if (s->TimerExpire && current_time >= s->TimerExpire) {
+ s->IntrStatus |= PCSTimeout;
+ rtl8139_update_irq(s);
+ }
+
+ /* Set QEMU timer only if needed that is
+ * - TimerInt <> 0 (we have a timer)
+ * - mask = 1 (we want an interrupt timer)
+ * - irq = 0 (irq is not already active)
+ * If any of above change we need to compute timer again
+ * Also we must check if timer is passed without QEMU timer
+ */
+ s->TimerExpire = 0;
+ if (!s->TimerInt) {
+ return;
+ }
+
+ pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
+ get_ticks_per_sec());
+ low_pci = pci_time & 0xffffffff;
+ pci_time = pci_time - low_pci + s->TimerInt;
+ if (low_pci >= s->TimerInt) {
+ pci_time += 0x100000000LL;
+ }
+ next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
+ PCI_FREQUENCY);
+ s->TimerExpire = next_time;
+
+ if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
+ qemu_mod_timer(s->timer, next_time);
+ }
+}
+
static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
{
RTL8139State *s = opaque;
- addr &= 0xfc;
-
switch (addr)
{
case RxMissed:
- DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
+ DPRINTF("RxMissed clearing on write\n");
s->RxMissed = 0;
break;
break;
case RxRingAddrLO:
- DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
+ DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
s->RxRingAddrLO = val;
break;
case RxRingAddrHI:
- DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
+ DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
s->RxRingAddrHI = val;
break;
case Timer:
- DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
- s->TCTR = 0;
- s->TCTR_base = qemu_get_clock(vm_clock);
+ DPRINTF("TCTR Timer reset on write\n");
+ s->TCTR_base = qemu_get_clock_ns(vm_clock);
+ rtl8139_set_next_tctr_time(s, s->TCTR_base);
break;
case FlashReg:
- DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
- s->TimerInt = val;
+ DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
+ if (s->TimerInt != val) {
+ s->TimerInt = val;
+ rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
+ }
break;
default:
- DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
+ DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
+ addr, val);
rtl8139_io_writeb(opaque, addr, val & 0xff);
rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
RTL8139State *s = opaque;
int ret;
- addr &= 0xff;
-
switch (addr)
{
case MAC0 ... MAC0+5:
case MediaStatus:
ret = 0xd0;
- DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
+ DPRINTF("MediaStatus read 0x%x\n", ret);
break;
case HltClk:
ret = s->clock_enabled;
- DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
+ DPRINTF("HltClk read 0x%x\n", ret);
break;
case PCIRevisionID:
ret = RTL8139_PCI_REVID;
- DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
+ DPRINTF("PCI Revision ID read 0x%x\n", ret);
break;
case TxThresh:
ret = s->TxThresh;
- DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
+ DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
break;
case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
ret = s->TxConfig >> 24;
- DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
+ DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
break;
default:
- DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
+ DPRINTF("not implemented read(b) addr=0x%x\n", addr);
ret = 0;
break;
}
RTL8139State *s = opaque;
uint32_t ret;
- addr &= 0xfe; /* mask lower bit */
-
switch (addr)
{
case IntrMask:
break;
case NWayAdvert:
ret = s->NWayAdvert;
- DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
+ DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
break;
case NWayLPAR:
ret = s->NWayLPAR;
- DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
+ DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
break;
case NWayExpansion:
ret = s->NWayExpansion;
- DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
+ DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
break;
case CpCmd:
break;
default:
- DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
+ DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
ret = rtl8139_io_readb(opaque, addr);
ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
- DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
+ DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
break;
}
RTL8139State *s = opaque;
uint32_t ret;
- addr &= 0xfc; /* also mask low 2 bits */
-
switch (addr)
{
case RxMissed:
ret = s->RxMissed;
- DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
+ DPRINTF("RxMissed read val=0x%08x\n", ret);
break;
case TxConfig:
case RxRingAddrLO:
ret = s->RxRingAddrLO;
- DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
+ DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
break;
case RxRingAddrHI:
ret = s->RxRingAddrHI;
- DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
+ DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
break;
case Timer:
- ret = s->TCTR;
- DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
+ ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
+ PCI_FREQUENCY, get_ticks_per_sec());
+ DPRINTF("TCTR Timer read val=0x%08x\n", ret);
break;
case FlashReg:
ret = s->TimerInt;
- DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
+ DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
break;
default:
- DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
+ DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
ret = rtl8139_io_readb(opaque, addr);
ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
- DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
+ DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
break;
}
static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap16(val);
-#endif
rtl8139_io_writew(opaque, addr & 0xFF, val);
}
static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
rtl8139_io_writel(opaque, addr & 0xFF, val);
}
static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap16(val);
-#endif
return val;
}
static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
return val;
}
-/* */
-
-static void rtl8139_save(QEMUFile* f,void* opaque)
+static int rtl8139_post_load(void *opaque, int version_id)
{
- RTL8139State* s=(RTL8139State*)opaque;
- unsigned int i;
-
- pci_device_save(s->pci_dev, f);
-
- qemu_put_buffer(f, s->phys, 6);
- qemu_put_buffer(f, s->mult, 8);
-
- for (i=0; i<4; ++i)
- {
- qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
- }
- for (i=0; i<4; ++i)
- {
- qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
- }
-
- qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
- qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
- qemu_put_be32s(f, &s->RxBufPtr);
- qemu_put_be32s(f, &s->RxBufAddr);
-
- qemu_put_be16s(f, &s->IntrStatus);
- qemu_put_be16s(f, &s->IntrMask);
-
- qemu_put_be32s(f, &s->TxConfig);
- qemu_put_be32s(f, &s->RxConfig);
- qemu_put_be32s(f, &s->RxMissed);
- qemu_put_be16s(f, &s->CSCR);
-
- qemu_put_8s(f, &s->Cfg9346);
- qemu_put_8s(f, &s->Config0);
- qemu_put_8s(f, &s->Config1);
- qemu_put_8s(f, &s->Config3);
- qemu_put_8s(f, &s->Config4);
- qemu_put_8s(f, &s->Config5);
-
- qemu_put_8s(f, &s->clock_enabled);
- qemu_put_8s(f, &s->bChipCmdState);
-
- qemu_put_be16s(f, &s->MultiIntr);
-
- qemu_put_be16s(f, &s->BasicModeCtrl);
- qemu_put_be16s(f, &s->BasicModeStatus);
- qemu_put_be16s(f, &s->NWayAdvert);
- qemu_put_be16s(f, &s->NWayLPAR);
- qemu_put_be16s(f, &s->NWayExpansion);
-
- qemu_put_be16s(f, &s->CpCmd);
- qemu_put_8s(f, &s->TxThresh);
-
- i = 0;
- qemu_put_be32s(f, &i); /* unused. */
- qemu_put_buffer(f, s->macaddr, 6);
- qemu_put_be32(f, s->rtl8139_mmio_io_addr);
-
- qemu_put_be32s(f, &s->currTxDesc);
- qemu_put_be32s(f, &s->currCPlusRxDesc);
- qemu_put_be32s(f, &s->currCPlusTxDesc);
- qemu_put_be32s(f, &s->RxRingAddrLO);
- qemu_put_be32s(f, &s->RxRingAddrHI);
-
- for (i=0; i<EEPROM_9346_SIZE; ++i)
- {
- qemu_put_be16s(f, &s->eeprom.contents[i]);
+ RTL8139State* s = opaque;
+ rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
+ if (version_id < 4) {
+ s->cplus_enabled = s->CpCmd != 0;
}
- qemu_put_be32(f, s->eeprom.mode);
- qemu_put_be32s(f, &s->eeprom.tick);
- qemu_put_8s(f, &s->eeprom.address);
- qemu_put_be16s(f, &s->eeprom.input);
- qemu_put_be16s(f, &s->eeprom.output);
-
- qemu_put_8s(f, &s->eeprom.eecs);
- qemu_put_8s(f, &s->eeprom.eesk);
- qemu_put_8s(f, &s->eeprom.eedi);
- qemu_put_8s(f, &s->eeprom.eedo);
- qemu_put_be32s(f, &s->TCTR);
- qemu_put_be32s(f, &s->TimerInt);
- qemu_put_be64(f, s->TCTR_base);
-
- RTL8139TallyCounters_save(f, &s->tally_counters);
-
- qemu_put_be32s(f, &s->cplus_enabled);
+ return 0;
}
-static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
+static bool rtl8139_hotplug_ready_needed(void *opaque)
{
- RTL8139State* s=(RTL8139State*)opaque;
- unsigned int i;
- int ret;
-
- /* just 2 versions for now */
- if (version_id > 4)
- return -EINVAL;
-
- if (version_id >= 3) {
- ret = pci_device_load(s->pci_dev, f);
- if (ret < 0)
- return ret;
- }
-
- /* saved since version 1 */
- qemu_get_buffer(f, s->phys, 6);
- qemu_get_buffer(f, s->mult, 8);
-
- for (i=0; i<4; ++i)
- {
- qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
- }
- for (i=0; i<4; ++i)
- {
- qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
- }
-
- qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
- qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
- qemu_get_be32s(f, &s->RxBufPtr);
- qemu_get_be32s(f, &s->RxBufAddr);
-
- qemu_get_be16s(f, &s->IntrStatus);
- qemu_get_be16s(f, &s->IntrMask);
-
- qemu_get_be32s(f, &s->TxConfig);
- qemu_get_be32s(f, &s->RxConfig);
- qemu_get_be32s(f, &s->RxMissed);
- qemu_get_be16s(f, &s->CSCR);
-
- qemu_get_8s(f, &s->Cfg9346);
- qemu_get_8s(f, &s->Config0);
- qemu_get_8s(f, &s->Config1);
- qemu_get_8s(f, &s->Config3);
- qemu_get_8s(f, &s->Config4);
- qemu_get_8s(f, &s->Config5);
-
- qemu_get_8s(f, &s->clock_enabled);
- qemu_get_8s(f, &s->bChipCmdState);
-
- qemu_get_be16s(f, &s->MultiIntr);
-
- qemu_get_be16s(f, &s->BasicModeCtrl);
- qemu_get_be16s(f, &s->BasicModeStatus);
- qemu_get_be16s(f, &s->NWayAdvert);
- qemu_get_be16s(f, &s->NWayLPAR);
- qemu_get_be16s(f, &s->NWayExpansion);
-
- qemu_get_be16s(f, &s->CpCmd);
- qemu_get_8s(f, &s->TxThresh);
-
- qemu_get_be32s(f, &i); /* unused. */
- qemu_get_buffer(f, s->macaddr, 6);
- s->rtl8139_mmio_io_addr=qemu_get_be32(f);
-
- qemu_get_be32s(f, &s->currTxDesc);
- qemu_get_be32s(f, &s->currCPlusRxDesc);
- qemu_get_be32s(f, &s->currCPlusTxDesc);
- qemu_get_be32s(f, &s->RxRingAddrLO);
- qemu_get_be32s(f, &s->RxRingAddrHI);
-
- for (i=0; i<EEPROM_9346_SIZE; ++i)
- {
- qemu_get_be16s(f, &s->eeprom.contents[i]);
- }
- s->eeprom.mode=qemu_get_be32(f);
- qemu_get_be32s(f, &s->eeprom.tick);
- qemu_get_8s(f, &s->eeprom.address);
- qemu_get_be16s(f, &s->eeprom.input);
- qemu_get_be16s(f, &s->eeprom.output);
-
- qemu_get_8s(f, &s->eeprom.eecs);
- qemu_get_8s(f, &s->eeprom.eesk);
- qemu_get_8s(f, &s->eeprom.eedi);
- qemu_get_8s(f, &s->eeprom.eedo);
-
- /* saved since version 2 */
- if (version_id >= 2)
- {
- qemu_get_be32s(f, &s->TCTR);
- qemu_get_be32s(f, &s->TimerInt);
- s->TCTR_base=qemu_get_be64(f);
-
- RTL8139TallyCounters_load(f, &s->tally_counters);
- }
- else
- {
- /* not saved, use default */
- s->TCTR = 0;
- s->TimerInt = 0;
- s->TCTR_base = 0;
+ return qdev_machine_modified();
+}
- RTL8139TallyCounters_clear(&s->tally_counters);
+static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
+ .name = "rtl8139/hotplug_ready",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_END_OF_LIST()
}
+};
- if (version_id >= 4) {
- qemu_get_be32s(f, &s->cplus_enabled);
- } else {
- s->cplus_enabled = s->CpCmd != 0;
+static void rtl8139_pre_save(void *opaque)
+{
+ RTL8139State* s = opaque;
+ int64_t current_time = qemu_get_clock_ns(vm_clock);
+
+ /* set IntrStatus correctly */
+ rtl8139_set_next_tctr_time(s, current_time);
+ s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
+ get_ticks_per_sec());
+ s->rtl8139_mmio_io_addr_dummy = 0;
+}
+
+static const VMStateDescription vmstate_rtl8139 = {
+ .name = "rtl8139",
+ .version_id = 4,
+ .minimum_version_id = 3,
+ .minimum_version_id_old = 3,
+ .post_load = rtl8139_post_load,
+ .pre_save = rtl8139_pre_save,
+ .fields = (VMStateField []) {
+ VMSTATE_PCI_DEVICE(dev, RTL8139State),
+ VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
+ VMSTATE_BUFFER(mult, RTL8139State),
+ VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
+ VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
+
+ VMSTATE_UINT32(RxBuf, RTL8139State),
+ VMSTATE_UINT32(RxBufferSize, RTL8139State),
+ VMSTATE_UINT32(RxBufPtr, RTL8139State),
+ VMSTATE_UINT32(RxBufAddr, RTL8139State),
+
+ VMSTATE_UINT16(IntrStatus, RTL8139State),
+ VMSTATE_UINT16(IntrMask, RTL8139State),
+
+ VMSTATE_UINT32(TxConfig, RTL8139State),
+ VMSTATE_UINT32(RxConfig, RTL8139State),
+ VMSTATE_UINT32(RxMissed, RTL8139State),
+ VMSTATE_UINT16(CSCR, RTL8139State),
+
+ VMSTATE_UINT8(Cfg9346, RTL8139State),
+ VMSTATE_UINT8(Config0, RTL8139State),
+ VMSTATE_UINT8(Config1, RTL8139State),
+ VMSTATE_UINT8(Config3, RTL8139State),
+ VMSTATE_UINT8(Config4, RTL8139State),
+ VMSTATE_UINT8(Config5, RTL8139State),
+
+ VMSTATE_UINT8(clock_enabled, RTL8139State),
+ VMSTATE_UINT8(bChipCmdState, RTL8139State),
+
+ VMSTATE_UINT16(MultiIntr, RTL8139State),
+
+ VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
+ VMSTATE_UINT16(BasicModeStatus, RTL8139State),
+ VMSTATE_UINT16(NWayAdvert, RTL8139State),
+ VMSTATE_UINT16(NWayLPAR, RTL8139State),
+ VMSTATE_UINT16(NWayExpansion, RTL8139State),
+
+ VMSTATE_UINT16(CpCmd, RTL8139State),
+ VMSTATE_UINT8(TxThresh, RTL8139State),
+
+ VMSTATE_UNUSED(4),
+ VMSTATE_MACADDR(conf.macaddr, RTL8139State),
+ VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
+
+ VMSTATE_UINT32(currTxDesc, RTL8139State),
+ VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
+ VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
+ VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
+ VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
+
+ VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
+ VMSTATE_INT32(eeprom.mode, RTL8139State),
+ VMSTATE_UINT32(eeprom.tick, RTL8139State),
+ VMSTATE_UINT8(eeprom.address, RTL8139State),
+ VMSTATE_UINT16(eeprom.input, RTL8139State),
+ VMSTATE_UINT16(eeprom.output, RTL8139State),
+
+ VMSTATE_UINT8(eeprom.eecs, RTL8139State),
+ VMSTATE_UINT8(eeprom.eesk, RTL8139State),
+ VMSTATE_UINT8(eeprom.eedi, RTL8139State),
+ VMSTATE_UINT8(eeprom.eedo, RTL8139State),
+
+ VMSTATE_UINT32(TCTR, RTL8139State),
+ VMSTATE_UINT32(TimerInt, RTL8139State),
+ VMSTATE_INT64(TCTR_base, RTL8139State),
+
+ VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
+ vmstate_tally_counters, RTL8139TallyCounters),
+
+ VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
+ VMSTATE_END_OF_LIST()
+ },
+ .subsections = (VMStateSubsection []) {
+ {
+ .vmsd = &vmstate_rtl8139_hotplug_ready,
+ .needed = rtl8139_hotplug_ready_needed,
+ }, {
+ /* empty */
+ }
}
-
- return 0;
-}
+};
/***********************************************************/
/* PCI RTL8139 definitions */
-typedef struct PCIRTL8139State {
- PCIDevice dev;
- RTL8139State rtl8139;
-} PCIRTL8139State;
-
-static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
-{
- PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
- RTL8139State *s = &d->rtl8139;
-
- cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
-}
-
-static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
-{
- PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
- RTL8139State *s = &d->rtl8139;
-
- register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
- register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
-
- register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
- register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
-
- register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
- register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
-}
-
-static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
- rtl8139_mmio_readb,
- rtl8139_mmio_readw,
- rtl8139_mmio_readl,
+static const MemoryRegionPortio rtl8139_portio[] = {
+ { 0, 0x100, 1, .read = rtl8139_ioport_readb, },
+ { 0, 0x100, 1, .write = rtl8139_ioport_writeb, },
+ { 0, 0x100, 2, .read = rtl8139_ioport_readw, },
+ { 0, 0x100, 2, .write = rtl8139_ioport_writew, },
+ { 0, 0x100, 4, .read = rtl8139_ioport_readl, },
+ { 0, 0x100, 4, .write = rtl8139_ioport_writel, },
+ PORTIO_END_OF_LIST()
};
-static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
- rtl8139_mmio_writeb,
- rtl8139_mmio_writew,
- rtl8139_mmio_writel,
+static const MemoryRegionOps rtl8139_io_ops = {
+ .old_portio = rtl8139_portio,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
-static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
-{
- int64_t next_time = current_time +
- muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
- if (next_time <= current_time)
- next_time = current_time + 1;
- return next_time;
-}
+static const MemoryRegionOps rtl8139_mmio_ops = {
+ .old_mmio = {
+ .read = {
+ rtl8139_mmio_readb,
+ rtl8139_mmio_readw,
+ rtl8139_mmio_readl,
+ },
+ .write = {
+ rtl8139_mmio_writeb,
+ rtl8139_mmio_writew,
+ rtl8139_mmio_writel,
+ },
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
-#ifdef RTL8139_ONBOARD_TIMER
static void rtl8139_timer(void *opaque)
{
RTL8139State *s = opaque;
- int is_timeout = 0;
-
- int64_t curr_time;
- uint32_t curr_tick;
-
if (!s->clock_enabled)
{
- DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
+ DPRINTF(">>> timer: clock is not running\n");
return;
}
- curr_time = qemu_get_clock(vm_clock);
-
- curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec);
-
- if (s->TimerInt && curr_tick >= s->TimerInt)
- {
- if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
- {
- is_timeout = 1;
- }
- }
-
- s->TCTR = curr_tick;
-
-// DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
+ s->IntrStatus |= PCSTimeout;
+ rtl8139_update_irq(s);
+ rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
+}
- if (is_timeout)
- {
- DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
- s->IntrStatus |= PCSTimeout;
- rtl8139_update_irq(s);
- }
+static void rtl8139_cleanup(VLANClientState *nc)
+{
+ RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
- qemu_mod_timer(s->timer,
- rtl8139_get_next_tctr_time(s,curr_time));
+ s->nic = NULL;
}
-#endif /* RTL8139_ONBOARD_TIMER */
-static void rtl8139_cleanup(VLANClientState *vc)
+static int pci_rtl8139_uninit(PCIDevice *dev)
{
- RTL8139State *s = vc->opaque;
+ RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
+ memory_region_destroy(&s->bar_io);
+ memory_region_destroy(&s->bar_mem);
if (s->cplus_txbuffer) {
- qemu_free(s->cplus_txbuffer);
+ g_free(s->cplus_txbuffer);
s->cplus_txbuffer = NULL;
}
-
-#ifdef RTL8139_ONBOARD_TIMER
qemu_del_timer(s->timer);
qemu_free_timer(s->timer);
-#endif
-
- unregister_savevm("rtl8139", s);
-}
-
-static int pci_rtl8139_uninit(PCIDevice *dev)
-{
- PCIRTL8139State *d = (PCIRTL8139State *)dev;
- RTL8139State *s = &d->rtl8139;
-
- cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
-
+ qemu_del_vlan_client(&s->nic->nc);
return 0;
}
-static void pci_rtl8139_init(PCIDevice *dev)
+static NetClientInfo net_rtl8139_info = {
+ .type = NET_CLIENT_TYPE_NIC,
+ .size = sizeof(NICState),
+ .can_receive = rtl8139_can_receive,
+ .receive = rtl8139_receive,
+ .cleanup = rtl8139_cleanup,
+};
+
+static int pci_rtl8139_init(PCIDevice *dev)
{
- PCIRTL8139State *d = (PCIRTL8139State *)dev;
- RTL8139State *s;
+ RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
uint8_t *pci_conf;
- d->dev.unregister = pci_rtl8139_uninit;
-
- pci_conf = d->dev.config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
- pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
- pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
- pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
- pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */
- pci_conf[0x3d] = 1; /* interrupt pin 0 */
- pci_conf[0x34] = 0xdc;
+ pci_conf = s->dev.config;
+ pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
+ /* TODO: start of capability list, but no capability
+ * list bit in status register, and offset 0xdc seems unused. */
+ pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
- s = &d->rtl8139;
+ memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
+ memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
+ pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
+ pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
- /* I/O handler for memory-mapped I/O */
- s->rtl8139_mmio_io_addr =
- cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s);
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
- pci_register_bar(&d->dev, 0, 0x100,
- PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);
-
- pci_register_bar(&d->dev, 1, 0x100,
- PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
-
- s->pci_dev = (PCIDevice *)d;
- qdev_get_macaddr(&dev->qdev, s->macaddr);
- qemu_register_reset(rtl8139_reset, s);
- rtl8139_reset(s);
- s->vc = qdev_get_vlan_client(&dev->qdev,
- rtl8139_can_receive, rtl8139_receive, NULL,
- rtl8139_cleanup, s);
+ /* prepare eeprom */
+ s->eeprom.contents[0] = 0x8129;
+#if 1
+ /* PCI vendor and device ID should be mirrored here */
+ s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
+ s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
+#endif
+ s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
+ s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
+ s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
- qemu_format_nic_info_str(s->vc, s->macaddr);
+ s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
+ dev->qdev.info->name, dev->qdev.id, s);
+ qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
s->cplus_txbuffer = NULL;
s->cplus_txbuffer_len = 0;
s->cplus_txbuffer_offset = 0;
- register_savevm("rtl8139", -1, 4, rtl8139_save, rtl8139_load, s);
+ s->TimerExpire = 0;
+ s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
+ rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
-#ifdef RTL8139_ONBOARD_TIMER
- s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
+ add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
- qemu_mod_timer(s->timer,
- rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
-#endif /* RTL8139_ONBOARD_TIMER */
+ return 0;
}
static PCIDeviceInfo rtl8139_info = {
- .qdev.name = "rtl8139",
- .qdev.size = sizeof(PCIRTL8139State),
- .init = pci_rtl8139_init,
+ .qdev.name = "rtl8139",
+ .qdev.size = sizeof(RTL8139State),
+ .qdev.reset = rtl8139_reset,
+ .qdev.vmsd = &vmstate_rtl8139,
+ .init = pci_rtl8139_init,
+ .exit = pci_rtl8139_uninit,
+ .romfile = "pxe-rtl8139.rom",
+ .vendor_id = PCI_VENDOR_ID_REALTEK,
+ .device_id = PCI_DEVICE_ID_REALTEK_8139,
+ .revision = RTL8139_PCI_REVID, /* >=0x20 is for 8139C+ */
+ .class_id = PCI_CLASS_NETWORK_ETHERNET,
+ .qdev.props = (Property[]) {
+ DEFINE_NIC_PROPERTIES(RTL8139State, conf),
+ DEFINE_PROP_END_OF_LIST(),
+ }
};
static void rtl8139_register_devices(void)
projects / mirror_qemu.git / blobdiff