* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include <stdio.h>
+#include "qemu/osdep.h"
#include "hw/hw.h"
-#include "hw/sh.h"
+#include "hw/sh4/sh.h"
#include "sysemu/sysemu.h"
-#include "hw/sh7750_regs.h"
-#include "hw/sh7750_regnames.h"
-#include "hw/sh_intc.h"
+#include "sh7750_regs.h"
+#include "sh7750_regnames.h"
+#include "hw/sh4/sh_intc.h"
#include "cpu.h"
-#include "exec/address-spaces.h"
+#include "exec/exec-all.h"
#define NB_DEVICES 4
MemoryRegion iomem_ffc;
MemoryRegion mmct_iomem;
/* CPU */
- CPUSH4State *cpu;
+ SuperHCPU *cpu;
/* Peripheral frequency in Hz */
uint32_t periph_freq;
/* SDRAM controller */
static inline int has_bcr3_and_bcr4(SH7750State * s)
{
- return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
+ return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4;
}
/**********************************************************************
I/O ports
static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
{
SH7750State *s = opaque;
+ SuperHCPUClass *scc;
switch (addr) {
case SH7750_BCR1_A7:
ignore_access("long read", addr);
return 0;
case SH7750_MMUCR_A7:
- return s->cpu->mmucr;
+ return s->cpu->env.mmucr;
case SH7750_PTEH_A7:
- return s->cpu->pteh;
+ return s->cpu->env.pteh;
case SH7750_PTEL_A7:
- return s->cpu->ptel;
+ return s->cpu->env.ptel;
case SH7750_TTB_A7:
- return s->cpu->ttb;
+ return s->cpu->env.ttb;
case SH7750_TEA_A7:
- return s->cpu->tea;
+ return s->cpu->env.tea;
case SH7750_TRA_A7:
- return s->cpu->tra;
+ return s->cpu->env.tra;
case SH7750_EXPEVT_A7:
- return s->cpu->expevt;
+ return s->cpu->env.expevt;
case SH7750_INTEVT_A7:
- return s->cpu->intevt;
+ return s->cpu->env.intevt;
case SH7750_CCR_A7:
return s->ccr;
case 0x1f000030: /* Processor version */
- return s->cpu->pvr;
+ scc = SUPERH_CPU_GET_CLASS(s->cpu);
+ return scc->pvr;
case 0x1f000040: /* Cache version */
- return s->cpu->cvr;
+ scc = SUPERH_CPU_GET_CLASS(s->cpu);
+ return scc->cvr;
case 0x1f000044: /* Processor revision */
- return s->cpu->prr;
+ scc = SUPERH_CPU_GET_CLASS(s->cpu);
+ return scc->prr;
default:
error_access("long read", addr);
abort();
return;
case SH7750_MMUCR_A7:
if (mem_value & MMUCR_TI) {
- cpu_sh4_invalidate_tlb(s->cpu);
+ cpu_sh4_invalidate_tlb(&s->cpu->env);
}
- s->cpu->mmucr = mem_value & ~MMUCR_TI;
+ s->cpu->env.mmucr = mem_value & ~MMUCR_TI;
return;
case SH7750_PTEH_A7:
/* If asid changes, clear all registered tlb entries. */
- if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
- tlb_flush(s->cpu, 1);
- s->cpu->pteh = mem_value;
- return;
+ if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
+ tlb_flush(CPU(s->cpu));
+ }
+ s->cpu->env.pteh = mem_value;
+ return;
case SH7750_PTEL_A7:
- s->cpu->ptel = mem_value;
- return;
+ s->cpu->env.ptel = mem_value;
+ return;
case SH7750_PTEA_A7:
- s->cpu->ptea = mem_value & 0x0000000f;
- return;
+ s->cpu->env.ptea = mem_value & 0x0000000f;
+ return;
case SH7750_TTB_A7:
- s->cpu->ttb = mem_value;
- return;
+ s->cpu->env.ttb = mem_value;
+ return;
case SH7750_TEA_A7:
- s->cpu->tea = mem_value;
- return;
+ s->cpu->env.tea = mem_value;
+ return;
case SH7750_TRA_A7:
- s->cpu->tra = mem_value & 0x000007ff;
- return;
+ s->cpu->env.tra = mem_value & 0x000007ff;
+ return;
case SH7750_EXPEVT_A7:
- s->cpu->expevt = mem_value & 0x000007ff;
- return;
+ s->cpu->env.expevt = mem_value & 0x000007ff;
+ return;
case SH7750_INTEVT_A7:
- s->cpu->intevt = mem_value & 0x000007ff;
- return;
+ s->cpu->env.intevt = mem_value & 0x000007ff;
+ return;
case SH7750_CCR_A7:
s->ccr = mem_value;
return;
}
}
+static uint64_t sh7750_mem_readfn(void *opaque, hwaddr addr, unsigned size)
+{
+ switch (size) {
+ case 1:
+ return sh7750_mem_readb(opaque, addr);
+ case 2:
+ return sh7750_mem_readw(opaque, addr);
+ case 4:
+ return sh7750_mem_readl(opaque, addr);
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void sh7750_mem_writefn(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
+{
+ switch (size) {
+ case 1:
+ sh7750_mem_writeb(opaque, addr, value);
+ break;
+ case 2:
+ sh7750_mem_writew(opaque, addr, value);
+ break;
+ case 4:
+ sh7750_mem_writel(opaque, addr, value);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static const MemoryRegionOps sh7750_mem_ops = {
- .old_mmio = {
- .read = {sh7750_mem_readb,
- sh7750_mem_readw,
- sh7750_mem_readl },
- .write = {sh7750_mem_writeb,
- sh7750_mem_writew,
- sh7750_mem_writel },
- },
+ .read = sh7750_mem_readfn,
+ .write = sh7750_mem_writefn,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,
};
/* do nothing */
break;
case MM_ITLB_ADDR:
- ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr);
+ ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr);
break;
case MM_ITLB_DATA:
- ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr);
+ ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr);
break;
case MM_OCACHE_ADDR:
case MM_OCACHE_DATA:
/* do nothing */
break;
case MM_UTLB_ADDR:
- ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr);
+ ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr);
break;
case MM_UTLB_DATA:
- ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr);
+ ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr);
break;
default:
abort();
/* do nothing */
break;
case MM_ITLB_ADDR:
- cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value);
+ cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value);
break;
case MM_ITLB_DATA:
- cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value);
+ cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value);
abort();
break;
case MM_OCACHE_ADDR:
/* do nothing */
break;
case MM_UTLB_ADDR:
- cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value);
+ cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value);
break;
case MM_UTLB_DATA:
- cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value);
+ cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value);
break;
default:
abort();
.endianness = DEVICE_NATIVE_ENDIAN,
};
-SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
+SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
{
SH7750State *s;
s = g_malloc0(sizeof(SH7750State));
s->cpu = cpu;
s->periph_freq = 60000000; /* 60MHz */
- memory_region_init_io(&s->iomem, &sh7750_mem_ops, s,
+ memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s,
"memory", 0x1fc01000);
- memory_region_init_alias(&s->iomem_1f0, "memory-1f0",
+ memory_region_init_alias(&s->iomem_1f0, NULL, "memory-1f0",
&s->iomem, 0x1f000000, 0x1000);
memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0);
- memory_region_init_alias(&s->iomem_ff0, "memory-ff0",
+ memory_region_init_alias(&s->iomem_ff0, NULL, "memory-ff0",
&s->iomem, 0x1f000000, 0x1000);
memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0);
- memory_region_init_alias(&s->iomem_1f8, "memory-1f8",
+ memory_region_init_alias(&s->iomem_1f8, NULL, "memory-1f8",
&s->iomem, 0x1f800000, 0x1000);
memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8);
- memory_region_init_alias(&s->iomem_ff8, "memory-ff8",
+ memory_region_init_alias(&s->iomem_ff8, NULL, "memory-ff8",
&s->iomem, 0x1f800000, 0x1000);
memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8);
- memory_region_init_alias(&s->iomem_1fc, "memory-1fc",
+ memory_region_init_alias(&s->iomem_1fc, NULL, "memory-1fc",
&s->iomem, 0x1fc00000, 0x1000);
memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc);
- memory_region_init_alias(&s->iomem_ffc, "memory-ffc",
+ memory_region_init_alias(&s->iomem_ffc, NULL, "memory-ffc",
&s->iomem, 0x1fc00000, 0x1000);
memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
- memory_region_init_io(&s->mmct_iomem, &sh7750_mmct_ops, s,
+ memory_region_init_io(&s->mmct_iomem, NULL, &sh7750_mmct_ops, s,
"cache-and-tlb", 0x08000000);
memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
_INTC_ARRAY(vectors),
_INTC_ARRAY(groups));
- cpu->intc_handle = &s->intc;
+ cpu->env.intc_handle = &s->intc;
sh_serial_init(sysmem, 0x1fe00000,
- 0, s->periph_freq, serial_hds[0],
+ 0, s->periph_freq, serial_hd(0),
s->intc.irqs[SCI1_ERI],
s->intc.irqs[SCI1_RXI],
s->intc.irqs[SCI1_TXI],
NULL);
sh_serial_init(sysmem, 0x1fe80000,
SH_SERIAL_FEAT_SCIF,
- s->periph_freq, serial_hds[1],
+ s->periph_freq, serial_hd(1),
s->intc.irqs[SCIF_ERI],
s->intc.irqs[SCIF_RXI],
s->intc.irqs[SCIF_TXI],
s->intc.irqs[TMU2_TUNI],
s->intc.irqs[TMU2_TICPI]);
- if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
+ if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_dma4),
_INTC_ARRAY(groups_dma4));
}
- if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
+ if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_dma8),
_INTC_ARRAY(groups_dma8));
}
- if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
+ if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_tmu34),
NULL, 0);
NULL, NULL);
}
- if (cpu->id & (SH_CPU_SH7751_ALL)) {
+ if (cpu->env.id & (SH_CPU_SH7751_ALL)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_pci),
_INTC_ARRAY(groups_pci));
}
- if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
+ if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_irlm),
NULL, 0);
qemu_irq sh7750_irl(SH7750State *s)
{
sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */
- return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
- 1)[0];
+ return qemu_allocate_irq(sh_intc_set_irl, sh_intc_source(&s->intc, IRL), 0);
}
projects / mirror_qemu.git / blobdiff