hw/9pfs: Update v9fs_lock to use coroutines

[mirror_qemu.git] / hw / sh_pci.c

diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index cc2f190529ebb66848f56f62095ce39b00e7fefd..cd8650143cbf425a11c1b81381e0e95fb149ba81 100644 (file)
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -21,24 +21,27 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
-#include "hw.h"
+#include "sysbus.h"
 #include "sh.h"
 #include "pci.h"
 #include "pci_host.h"
-#include "sh_pci.h"
 #include "bswap.h"
+#include "exec-memory.h"
 
-typedef struct {
+typedef struct SHPCIState {
+    SysBusDevice busdev;
     PCIBus *bus;
     PCIDevice *dev;
+    qemu_irq irq[4];
+    int memconfig;
     uint32_t par;
     uint32_t mbr;
     uint32_t iobr;
-} SHPCIC;
+} SHPCIState;
 
 static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
 {
-    SHPCIC *pcic = p;
+    SHPCIState *pcic = p;
     switch(addr) {
     case 0 ... 0xfc:
         cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
@@ -54,7 +57,7 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
             cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000,
                                          IO_MEM_UNASSIGNED);
             pcic->iobr = val & 0xfffc0001;
-            isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000, 0);
+            isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000);
         }
         break;
     case 0x220:
@@ -65,7 +68,7 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
 
 static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
 {
-    SHPCIC *pcic = p;
+    SHPCIState *pcic = p;
     switch(addr) {
     case 0 ... 0xfc:
         return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
@@ -91,31 +94,72 @@ static MemOp sh_pci_reg = {
     { NULL, NULL, sh_pci_reg_write },
 };
 
-PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
-                            void *opaque, int devfn_min, int nirq)
+static int sh_pci_map_irq(PCIDevice *d, int irq_num)
+{
+    return (d->devfn >> 3);
+}
+
+static void sh_pci_set_irq(void *opaque, int irq_num, int level)
+{
+    qemu_irq *pic = opaque;
+
+    qemu_set_irq(pic[irq_num], level);
+}
+
+static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base)
+{
+    SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
+
+    cpu_register_physical_memory(P4ADDR(base), 0x224, s->memconfig);
+    cpu_register_physical_memory(A7ADDR(base), 0x224, s->memconfig);
+
+    s->iobr = 0xfe240000;
+    isa_mmio_init(s->iobr, 0x40000);
+}
+
+static int sh_pci_init_device(SysBusDevice *dev)
+{
+    SHPCIState *s;
+    int i;
+
+    s = FROM_SYSBUS(SHPCIState, dev);
+    for (i = 0; i < 4; i++) {
+        sysbus_init_irq(dev, &s->irq[i]);
+    }
+    s->bus = pci_register_bus(&s->busdev.qdev, "pci",
+                              sh_pci_set_irq, sh_pci_map_irq,
+                              s->irq,
+                              get_system_memory(),
+                              get_system_io(),
+                              PCI_DEVFN(0, 0), 4);
+    s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w,
+                                          s, DEVICE_NATIVE_ENDIAN);
+    sysbus_init_mmio_cb(dev, 0x224, sh_pci_map);
+    s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host");
+    return 0;
+}
+
+static int sh_pci_host_init(PCIDevice *d)
+{
+    pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
+    pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
+                 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
+    return 0;
+}
+
+static PCIDeviceInfo sh_pci_host_info = {
+    .qdev.name = "sh_pci_host",
+    .qdev.size = sizeof(PCIDevice),
+    .init      = sh_pci_host_init,
+    .vendor_id = PCI_VENDOR_ID_HITACHI,
+    .device_id = PCI_DEVICE_ID_HITACHI_SH7751R,
+};
+
+static void sh_pci_register_devices(void)
 {
-    SHPCIC *p;
-    int reg;
-
-    p = qemu_mallocz(sizeof(SHPCIC));
-    p->bus = pci_register_bus(NULL, "pci",
-                              set_irq, map_irq, opaque, devfn_min, nirq);
-
-    p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
-                                 -1, NULL, NULL);
-    reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p);
-    cpu_register_physical_memory(0x1e200000, 0x224, reg);
-    cpu_register_physical_memory(0xfe200000, 0x224, reg);
-
-    p->iobr = 0xfe240000;
-    isa_mmio_init(p->iobr, 0x40000, 0);
-
-    pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI);
-    pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R);
-    p->dev->config[0x04] = 0x80;
-    p->dev->config[0x05] = 0x00;
-    p->dev->config[0x06] = 0x90;
-    p->dev->config[0x07] = 0x02;
-
-    return p->bus;
+    sysbus_register_dev("sh_pci", sizeof(SHPCIState),
+                        sh_pci_init_device);
+    pci_qdev_register(&sh_pci_host_info);
 }
+
+device_init(sh_pci_register_devices)