mask all interrupts when MASTER_DISABLE is set

[mirror_qemu.git] / hw / slavio_intctl.c

diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
index b76d3acadd7b1858ae5d348d7bd4aba6128796a2..10362a36550243b7038746f320155ed647134665 100644 (file)
--- a/hw/slavio_intctl.c
+++ b/hw/slavio_intctl.c
@@ -289,9 +289,12 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
             }
         }
 
-        /* Level 15 and CPU timer interrupts are not maskable */
-        pil_pending |= s->slaves[i].intreg_pending &
-            (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
+        /* Level 15 and CPU timer interrupts are only masked when
+           the MASTER_DISABLE bit is set */
+        if (!(s->intregm_disabled & MASTER_DISABLE)) {
+            pil_pending |= s->slaves[i].intreg_pending &
+                (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
+        }
 
         /* Add soft interrupts */
         pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;