PXA: Account for offset from page start in a subpage mapping.

[mirror_qemu.git] / hw / sm501.c

diff --git a/hw/sm501.c b/hw/sm501.c
index 64d5731e46ee6220d4051a3f2b5a81058b4a54c3..de6107521c75d38d70b058147f10d17c465791b8 100644 (file)
--- a/hw/sm501.c
+++ b/hw/sm501.c
@@ -529,12 +529,10 @@ static uint32_t get_local_mem_size_index(uint32_t size)
 static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
 {
     SM501State * s = (SM501State *)opaque;
-    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
     uint32_t ret = 0;
-    SM501_DPRINTF("sm501 system config regs : read addr=%x, offset=%x\n",
-                 addr, offset);
+    SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
 
-    switch(offset) {
+    switch(addr) {
     case SM501_SYSTEM_CONTROL:
        ret = s->system_control;
        break;
@@ -573,7 +571,7 @@ static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
 
     default:
        printf("sm501 system config : not implemented register read."
-              " addr=%x, offset=%x\n", addr, offset);
+              " addr=%x\n", (int)addr);
        assert(0);
     }
 
@@ -584,11 +582,10 @@ static void sm501_system_config_write(void *opaque,
                                      target_phys_addr_t addr, uint32_t value)
 {
     SM501State * s = (SM501State *)opaque;
-    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
-    SM501_DPRINTF("sm501 system config regs : write addr=%x, ofs=%x, val=%x\n",
-                 addr, offset, value);
+    SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
+                 addr, value);
 
-    switch(offset) {
+    switch(addr) {
     case SM501_SYSTEM_CONTROL:
        s->system_control = value & 0xE300B8F7;
        break;
@@ -624,7 +621,7 @@ static void sm501_system_config_write(void *opaque,
 
     default:
        printf("sm501 system config : not implemented register write."
-              " addr=%x, val=%x\n", addr, value);
+              " addr=%x, val=%x\n", (int)addr, value);
        assert(0);
     }
 }
@@ -641,16 +638,13 @@ static CPUWriteMemoryFunc *sm501_system_config_writefn[] = {
     &sm501_system_config_write,
 };
 
-static uint32_t sm501_disp_ctrl_read(void *opaque,
-                                             target_phys_addr_t addr)
+static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr)
 {
     SM501State * s = (SM501State *)opaque;
-    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC);
     uint32_t ret = 0;
-    SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x, offset=%x\n",
-                 addr, offset);
+    SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
 
-    switch(offset) {
+    switch(addr) {
 
     case SM501_DC_PANEL_CONTROL:
        ret = s->dc_panel_control;
@@ -727,7 +721,7 @@ static uint32_t sm501_disp_ctrl_read(void *opaque,
 
     default:
        printf("sm501 disp ctrl : not implemented register read."
-              " addr=%x, offset=%x\n", addr, offset);
+              " addr=%x\n", (int)addr);
        assert(0);
     }
 
@@ -739,11 +733,10 @@ static void sm501_disp_ctrl_write(void *opaque,
                                           uint32_t value)
 {
     SM501State * s = (SM501State *)opaque;
-    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC);
-    SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, ofs=%x, val=%x\n",
-                 addr, offset, value);
+    SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
+                 addr, value);
 
-    switch(offset) {
+    switch(addr) {
     case SM501_DC_PANEL_CONTROL:
        s->dc_panel_control = value & 0x0FFF73FF;
        break;
@@ -832,7 +825,7 @@ static void sm501_disp_ctrl_write(void *opaque,
 
     default:
        printf("sm501 disp ctrl : not implemented register write."
-              " addr=%x, val=%x\n", addr, value);
+              " addr=%x, val=%x\n", (int)addr, value);
        assert(0);
     }
 }
@@ -852,31 +845,27 @@ static CPUWriteMemoryFunc *sm501_disp_ctrl_writefn[] = {
 static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
 {
     SM501State * s = (SM501State *)opaque;
-    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET
-                             + SM501_DC + SM501_DC_PANEL_PALETTE);
-    SM501_DPRINTF("sm501 palette read addr=%x, offset=%x\n", addr, offset);
+    SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
 
     /* TODO : consider BYTE/WORD access */
     /* TODO : consider endian */
 
-    assert(0 <= offset && offset < 0x400 * 3);
-    return *(uint32_t*)&s->dc_palette[offset];
+    assert(0 <= addr && addr < 0x400 * 3);
+    return *(uint32_t*)&s->dc_palette[addr];
 }
 
 static void sm501_palette_write(void *opaque,
                                target_phys_addr_t addr, uint32_t value)
 {
     SM501State * s = (SM501State *)opaque;
-    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET
-                             + SM501_DC + SM501_DC_PANEL_PALETTE);
-    SM501_DPRINTF("sm501 palette write addr=%x, ofs=%x, val=%x\n",
-                 addr, offset, value);
+    SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
+                 (int)addr, value);
 
     /* TODO : consider BYTE/WORD access */
     /* TODO : consider endian */
 
-    assert(0 <= offset && offset < 0x400 * 3);
-    *(uint32_t*)&s->dc_palette[offset] = value;
+    assert(0 <= addr && addr < 0x400 * 3);
+    *(uint32_t*)&s->dc_palette[addr] = value;
 }
 
 static CPUReadMemoryFunc *sm501_palette_readfn[] = {