#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
-#include "qemu-common.h"
+#include "qemu/datadir.h"
#include "cpu.h"
+#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
-#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_host.h"
#include "hw/qdev-properties.h"
#include "hw/pci-host/sabre.h"
#include "hw/char/serial.h"
-#include "hw/char/parallel.h"
+#include "hw/char/parallel-isa.h"
#include "hw/rtc/m48t59.h"
#include "migration/vmstate.h"
#include "hw/input/i8042.h"
#include "hw/fw-path-provider.h"
#include "elf.h"
#include "trace.h"
+#include "qom/object.h"
#define KERNEL_LOAD_ADDR 0x00404000
#define CMDLINE_ADDR 0x003ff000
#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
#define PROM_FILENAME "openbios-sparc64"
#define NVRAM_SIZE 0x2000
-#define MAX_IDE_BUS 2
#define BIOS_CFG_IOPORT 0x510
#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
uint64_t console_serial_base;
};
-typedef struct EbusState {
+struct EbusState {
/*< private >*/
PCIDevice parent_obj;
ISABus *isa_bus;
- qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
+ qemu_irq *isa_irqs_in;
+ qemu_irq isa_irqs_out[ISA_NUM_IRQS];
uint64_t console_serial_base;
MemoryRegion bar0;
MemoryRegion bar1;
-} EbusState;
+};
#define TYPE_EBUS "ebus"
-#define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
+OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS)
const char *fw_cfg_arch_key_name(uint16_t key)
{
memset(image, '\0', sizeof(image));
/* OpenBIOS nvram variables partition */
- sysp_end = chrp_nvram_create_system_partition(image, 0);
+ sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
/* Free space partition */
chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
} ResetData;
#define TYPE_SUN4U_POWER "power"
-#define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
+OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER)
-typedef struct PowerDevice {
+struct PowerDevice {
SysBusDevice parent_obj;
MemoryRegion power_mmio;
-} PowerDevice;
+};
/* Power */
static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
static void ebus_isa_irq_handler(void *opaque, int n, int level)
{
EbusState *s = EBUS(opaque);
- qemu_irq irq = s->isa_bus_irqs[n];
+ qemu_irq irq = s->isa_irqs_out[n];
/* Pass ISA bus IRQs onto their gpio equivalent */
trace_ebus_isa_irq_handler(n, level);
ISADevice *isa_dev;
SysBusDevice *sbd;
DeviceState *dev;
- qemu_irq *isa_irq;
DriveInfo *fd[MAX_FD];
int i;
}
/* ISA bus */
- isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
- isa_bus_irqs(s->isa_bus, isa_irq);
- qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
+ s->isa_irqs_in = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
+ isa_bus_register_input_irqs(s->isa_bus, s->isa_irqs_in);
+ qdev_init_gpio_out_named(DEVICE(s), s->isa_irqs_out, "isa-irq",
ISA_NUM_IRQS);
/* Serial ports */
parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
/* Keyboard */
- isa_create_simple(s->isa_bus, "i8042");
+ isa_create_simple(s->isa_bus, TYPE_I8042);
/* Floppy */
for (i = 0; i < MAX_FD; i++) {
pci_dev->config[0x09] = 0x00; // programming i/f
pci_dev->config[0x0D] = 0x0a; // latency_timer
- memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
- 0, 0x1000000);
+ memory_region_init_alias(&s->bar0, OBJECT(s), "bar0",
+ pci_address_space_io(pci_dev), 0, 0x1000000);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
- memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
- 0, 0x8000);
+ memory_region_init_alias(&s->bar1, OBJECT(s), "bar1",
+ pci_address_space_io(pci_dev), 0, 0x8000);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
}
};
#define TYPE_OPENPROM "openprom"
-#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
+typedef struct PROMState PROMState;
+DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
+ TYPE_OPENPROM)
-typedef struct PROMState {
+struct PROMState {
SysBusDevice parent_obj;
MemoryRegion prom;
-} PROMState;
+};
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
{
{
PROMState *s = OPENPROM(ds);
SysBusDevice *dev = SYS_BUS_DEVICE(ds);
- Error *local_err = NULL;
- memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
- PROM_SIZE_MAX, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
+ if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
+ PROM_SIZE_MAX, errp)) {
return;
}
#define TYPE_SUN4U_MEMORY "memory"
-#define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
+typedef struct RamDevice RamDevice;
+DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM,
+ TYPE_SUN4U_MEMORY)
-typedef struct RamDevice {
+struct RamDevice {
SysBusDevice parent_obj;
MemoryRegion ram;
uint64_t size;
-} RamDevice;
+};
/* System RAM */
static void ram_realize(DeviceState *dev, Error **errp)
MachineState *machine,
const struct hwdef *hwdef)
{
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
SPARCCPU *cpu;
Nvram *nvram;
unsigned int i;
/* set up devices */
ram_init(0, machine->ram_size);
- prom_init(hwdef->prom_addr, bios_name);
+ prom_init(hwdef->prom_addr, machine->firmware);
/* Init sabre (PCI host bridge) */
- sabre = SABRE_DEVICE(qdev_new(TYPE_SABRE));
+ sabre = SABRE(qdev_new(TYPE_SABRE));
qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu),
&error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
+ /* sabre_config */
+ sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE);
+ /* PCI configuration space */
+ sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL);
+ /* pci_ioport */
+ sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL);
+
/* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) {
qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
/* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
reserved (leaving no slots free after on-board devices) however slots
0-3 are free on busB */
- pci_bus->slot_reserved_mask = 0xfffffffc;
- pci_busA->slot_reserved_mask = 0xfffffff1;
- pci_busB->slot_reserved_mask = 0xfffffff0;
+ pci_bus_set_slot_reserved_mask(pci_bus, 0xfffffffc);
+ pci_bus_set_slot_reserved_mask(pci_busA, 0xfffffff1);
+ pci_bus_set_slot_reserved_mask(pci_busB, 0xfffffff0);
- ebus = pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS);
+ ebus = pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_EBUS);
qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
hwdef->console_serial_base);
pci_realize_and_unref(ebus, pci_busA, &error_fatal);
switch (vga_interface_type) {
case VGA_STD:
pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
+ vga_interface_created = true;
break;
case VGA_NONE:
break;
PCIBus *bus;
nd = &nd_table[i];
- if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
+ if (!nd->model || strcmp(nd->model, mc->default_nic) == 0) {
if (!onboard_nic) {
- pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1),
- true, "sunhme");
+ pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), mc->default_nic);
bus = pci_busA;
memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
onboard_nic = true;
} else {
- pci_dev = pci_new(-1, "sunhme");
+ pci_dev = pci_new(-1, mc->default_nic);
bus = pci_busB;
}
} else {
pci_ide_create_devs(pci_dev);
/* Map NVRAM into I/O (ebus) space */
- nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
- s = SYS_BUS_DEVICE(nvram);
+ dev = qdev_new("sysbus-m48t59");
+ qdev_prop_set_int32(dev, "base-year", 1968);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
sysbus_mmio_get_region(s, 0));
+ nvram = NVRAM(dev);
initrd_size = 0;
initrd_addr = 0;
kernel_size = sun4u_load_kernel(machine->kernel_filename,
machine->initrd_filename,
- ram_size, &initrd_size, &initrd_addr,
+ machine->ram_size, &initrd_size, &initrd_addr,
&kernel_addr, &kernel_entry);
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
- machine->boot_order,
+ machine->boot_config.order,
kernel_addr, kernel_size,
machine->kernel_cmdline,
initrd_addr, initrd_size,
fw_cfg = FW_CFG(dev);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
- fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
}
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
- fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
DeviceState *dev)
{
PCIDevice *pci;
- IDEBus *ide_bus;
- IDEState *ide_s;
- int bus_id;
if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
pci = PCI_DEVICE(dev);
}
}
- if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
- ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
- ide_s = idebus_active_if(ide_bus);
- bus_id = ide_bus->bus_id;
-
- if (ide_s->drive_kind == IDE_CD) {
- return g_strdup_printf("ide@%x/cdrom", bus_id);
- }
-
- return g_strdup_printf("ide@%x/disk", bus_id);
- }
-
if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
return g_strdup("disk");
}
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
mc->ignore_boot_device_suffixes = true;
mc->default_display = "std";
+ mc->default_nic = "sunhme";
+ mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
fwc->get_dev_path = sun4u_fw_dev_path;
}
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
mc->default_display = "std";
+ mc->default_nic = "sunhme";
+ mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
}
static const TypeInfo sun4v_type = {
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