#include "block.h"
#include "audio/audio.h"
#include "boards.h"
+#include "blockdev.h"
+#include "sysbus.h"
#undef REG_FMT
#define REG_FMT "0x%02lx"
#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
typedef struct {
+ SysBusDevice busdev;
NANDFlashState *nand;
uint8_t ctl;
+ uint8_t manf_id;
+ uint8_t chip_id;
ECCState ecc;
} SLNANDState;
}
}
-static void sl_save(QEMUFile *f, void *opaque)
-{
- SLNANDState *s = (SLNANDState *) opaque;
-
- qemu_put_8s(f, &s->ctl);
- ecc_put(f, &s->ecc);
-}
-
-static int sl_load(QEMUFile *f, void *opaque, int version_id)
-{
- SLNANDState *s = (SLNANDState *) opaque;
-
- qemu_get_8s(f, &s->ctl);
- ecc_get(f, &s->ecc);
-
- return 0;
-}
-
enum {
FLASH_128M,
FLASH_1024M,
};
+static CPUReadMemoryFunc * const sl_readfn[] = {
+ sl_readb,
+ sl_readb,
+ sl_readl,
+};
+static CPUWriteMemoryFunc * const sl_writefn[] = {
+ sl_writeb,
+ sl_writeb,
+ sl_writeb,
+};
+
static void sl_flash_register(PXA2xxState *cpu, int size)
{
+ DeviceState *dev;
+
+ dev = qdev_create(NULL, "sl-nand");
+
+ qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
+ if (size == FLASH_128M)
+ qdev_prop_set_uint8(dev, "chip_id", 0x73);
+ else if (size == FLASH_1024M)
+ qdev_prop_set_uint8(dev, "chip_id", 0xf1);
+
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(sysbus_from_qdev(dev), 0, FLASH_BASE);
+}
+
+static int sl_nand_init(SysBusDevice *dev) {
int iomemtype;
SLNANDState *s;
- CPUReadMemoryFunc * const sl_readfn[] = {
- sl_readb,
- sl_readb,
- sl_readl,
- };
- CPUWriteMemoryFunc * const sl_writefn[] = {
- sl_writeb,
- sl_writeb,
- sl_writeb,
- };
-
- s = (SLNANDState *) qemu_mallocz(sizeof(SLNANDState));
+
+ s = FROM_SYSBUS(SLNANDState, dev);
+
s->ctl = 0;
- if (size == FLASH_128M)
- s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
- else if (size == FLASH_1024M)
- s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
+ s->nand = nand_init(s->manf_id, s->chip_id);
iomemtype = cpu_register_io_memory(sl_readfn,
- sl_writefn, s);
- cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype);
+ sl_writefn, s, DEVICE_NATIVE_ENDIAN);
+
+ sysbus_init_mmio(dev, 0x40, iomemtype);
- register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
+ return 0;
}
/* Spitz Keyboard */
s->fifopos = 0;
}
- qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
+ qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) +
+ get_ticks_per_sec() / 32);
}
static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
spitz_keyboard_pre_map(s);
qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
- register_savevm("spitz_keyboard", 0, 0,
+ register_savevm(NULL, "spitz_keyboard", 0, 0,
spitz_keyboard_save, spitz_keyboard_load, s);
}
typedef struct {
SSISlave ssidev;
- int bl_intensity;
- int bl_power;
+ uint32_t bl_intensity;
+ uint32_t bl_power;
} SpitzLCDTG;
static void spitz_bl_update(SpitzLCDTG *s)
return 0;
}
-static void spitz_lcdtg_save(QEMUFile *f, void *opaque)
-{
- SpitzLCDTG *s = (SpitzLCDTG *)opaque;
- qemu_put_be32(f, s->bl_intensity);
- qemu_put_be32(f, s->bl_power);
-}
-
-static int spitz_lcdtg_load(QEMUFile *f, void *opaque, int version_id)
-{
- SpitzLCDTG *s = (SpitzLCDTG *)opaque;
- s->bl_intensity = qemu_get_be32(f);
- s->bl_power = qemu_get_be32(f);
- return 0;
-}
-
static int spitz_lcdtg_init(SSISlave *dev)
{
SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
s->bl_power = 0;
s->bl_intensity = 0x20;
- register_savevm("spitz-lcdtg", -1, 1,
- spitz_lcdtg_save, spitz_lcdtg_load, s);
return 0;
}
typedef struct {
SSISlave ssidev;
SSIBus *bus[3];
- int enable[3];
+ uint32_t enable[3];
} CorgiSSPState;
static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
}
-static void spitz_ssp_save(QEMUFile *f, void *opaque)
-{
- CorgiSSPState *s = (CorgiSSPState *)opaque;
- int i;
-
- for (i = 0; i < 3; i++) {
- qemu_put_be32(f, s->enable[i]);
- }
-}
-
-static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
-{
- CorgiSSPState *s = (CorgiSSPState *)opaque;
- int i;
-
- if (version_id != 1) {
- return -EINVAL;
- }
- for (i = 0; i < 3; i++) {
- s->enable[i] = qemu_get_be32(f);
- }
- return 0;
-}
-
static int corgi_ssp_init(SSISlave *dev)
{
CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");
- register_savevm("spitz_ssp", -1, 1, spitz_ssp_save, spitz_ssp_load, s);
return 0;
}
mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
bus = qdev_get_child_bus(mux, "ssi0");
- dev = ssi_create_slave(bus, "spitz-lcdtg");
+ ssi_create_slave(bus, "spitz-lcdtg");
bus = qdev_get_child_bus(mux, "ssi1");
dev = ssi_create_slave(bus, "ads7846");
#define SPITZ_GPIO_WM 5
-#ifdef HAS_AUDIO
static void spitz_wm8750_addr(void *opaque, int line, int level)
{
i2c_slave *wm = (i2c_slave *) opaque;
else
i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
}
-#endif
static void spitz_i2c_setup(PXA2xxState *cpu)
{
/* Attach the CPU on one end of our I2C bus. */
i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
-#ifdef HAS_AUDIO
DeviceState *wm;
/* Attach a WM8750 to the bus */
cpu->i2s->codec_out = wm8750_dac_dat;
cpu->i2s->codec_in = wm8750_adc_dat;
wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
-#endif
}
static void spitz_akita_i2c_setup(PXA2xxState *cpu)
#define SPITZ_SCP2_MIC_BIAS 9
static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
- ScoopInfo *scp0, ScoopInfo *scp1)
+ DeviceState *scp0, DeviceState *scp1)
{
qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
- scoop_gpio_out_set(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
- scoop_gpio_out_set(scp0, SPITZ_SCP_JK_B, outsignals[1]);
- scoop_gpio_out_set(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
- scoop_gpio_out_set(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
+ qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
+ qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
+ qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
+ qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
if (scp1) {
- scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
- scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
+ qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
+ qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
}
- scoop_gpio_out_set(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
+ qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
}
#define SPITZ_GPIO_HSYNC 22
const char *cpu_model, enum spitz_model_e model, int arm_id)
{
PXA2xxState *cpu;
- ScoopInfo *scp0, *scp1 = NULL;
+ DeviceState *scp0, *scp1 = NULL;
if (!cpu_model)
cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
cpu_register_physical_memory(0, SPITZ_ROM,
- qemu_ram_alloc(SPITZ_ROM) | IO_MEM_ROM);
+ qemu_ram_alloc(NULL, "spitz.rom", SPITZ_ROM) | IO_MEM_ROM);
/* Setup peripherals */
spitz_keyboard_register(cpu);
spitz_ssp_attach(cpu);
- scp0 = scoop_init(cpu, 0, 0x10800000);
+ scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
if (model != akita) {
- scp1 = scoop_init(cpu, 1, 0x08800040);
+ scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
}
spitz_scoop_gpio_setup(cpu, scp0, scp1);
/* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
spitz_microdrive_attach(cpu, 0);
- /* Setup initial (reset) machine state */
- cpu->env->regs[15] = spitz_binfo.loader_start;
-
spitz_binfo.kernel_filename = kernel_filename;
spitz_binfo.kernel_cmdline = kernel_cmdline;
spitz_binfo.initrd_filename = initrd_filename;
machine_init(spitz_machine_init);
+static VMStateDescription vmstate_sl_nand_info = {
+ .name = "sl-nand",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT8(ctl, SLNANDState),
+ VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+static SysBusDeviceInfo sl_nand_info = {
+ .init = sl_nand_init,
+ .qdev.name = "sl-nand",
+ .qdev.size = sizeof(SLNANDState),
+ .qdev.vmsd = &vmstate_sl_nand_info,
+ .qdev.props = (Property []) {
+ DEFINE_PROP_UINT8("manf_id", SLNANDState, manf_id, NAND_MFR_SAMSUNG),
+ DEFINE_PROP_UINT8("chip_id", SLNANDState, chip_id, 0xf1),
+ DEFINE_PROP_END_OF_LIST(),
+ },
+};
+
+static const VMStateDescription vmstate_corgi_ssp_regs = {
+ .name = "corgi-ssp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
static SSISlaveInfo corgi_ssp_info = {
.qdev.name = "corgi-ssp",
.qdev.size = sizeof(CorgiSSPState),
+ .qdev.vmsd = &vmstate_corgi_ssp_regs,
.init = corgi_ssp_init,
.transfer = corgi_ssp_transfer
};
+static const VMStateDescription vmstate_spitz_lcdtg_regs = {
+ .name = "spitz-lcdtg",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
+ VMSTATE_UINT32(bl_power, SpitzLCDTG),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
static SSISlaveInfo spitz_lcdtg_info = {
.qdev.name = "spitz-lcdtg",
.qdev.size = sizeof(SpitzLCDTG),
+ .qdev.vmsd = &vmstate_spitz_lcdtg_regs,
.init = spitz_lcdtg_init,
.transfer = spitz_lcdtg_transfer
};
{
ssi_register_slave(&corgi_ssp_info);
ssi_register_slave(&spitz_lcdtg_info);
+ sysbus_register_withprop(&sl_nand_info);
}
device_init(spitz_register_devices)
projects / mirror_qemu.git / blobdiff