*/
#include "qemu/osdep.h"
+#include "hw/irq.h"
#include "hw/ssi/imx_spi.h"
-#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
#include "qemu/log.h"
+#include "qemu/module.h"
#ifndef DEBUG_IMX_SPI
#define DEBUG_IMX_SPI 0
case ECSPI_MSGDATA:
return "ECSPI_MSGDATA";
default:
- sprintf(unknown, "%d ?", reg);
+ sprintf(unknown, "%u ?", reg);
return unknown;
}
}
.name = TYPE_IMX_SPI,
.version_id = 1,
.minimum_version_id = 1,
- .fields = (VMStateField[]) {
+ .fields = (const VMStateField[]) {
VMSTATE_FIFO32(tx_fifo, IMXSPIState),
VMSTATE_FIFO32(rx_fifo, IMXSPIState),
VMSTATE_INT16(burst_length, IMXSPIState),
static uint32_t imx_spi_burst_length(IMXSPIState *s)
{
- return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+ uint32_t burst;
+
+ burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+ if (burst % 8) {
+ burst = ROUND_UP(burst, 8);
+ }
+
+ return burst;
}
static bool imx_spi_is_enabled(IMXSPIState *s)
while (!fifo32_is_empty(&s->tx_fifo)) {
int tx_burst = 0;
- int index = 0;
if (s->burst_length <= 0) {
s->burst_length = imx_spi_burst_length(s);
DPRINTF("data tx:0x%08x\n", tx);
- tx_burst = MIN(s->burst_length, 32);
+ tx_burst = (s->burst_length % 32) ? : 32;
rx = 0;
- while (tx_burst) {
- uint8_t byte = tx & 0xff;
+ while (tx_burst > 0) {
+ uint8_t byte = tx >> (tx_burst - 8);
DPRINTF("writing 0x%02x\n", (uint32_t)byte);
DPRINTF("0x%02x read\n", (uint32_t)byte);
- tx = tx >> 8;
- rx |= (byte << (index * 8));
+ rx = (rx << 8) | byte;
/* Remove 8 bits from the actual burst */
tx_burst -= 8;
s->burst_length -= 8;
- index++;
}
DPRINTF("data rx:0x%08x\n", rx);
if (fifo32_is_full(&s->rx_fifo)) {
s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
} else {
- fifo32_push(&s->rx_fifo, (uint8_t)rx);
+ fifo32_push(&s->rx_fifo, rx);
}
if (s->burst_length <= 0) {
- s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
-
if (!imx_spi_is_multiple_master_burst(s)) {
s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
break;
if (fifo32_is_empty(&s->tx_fifo)) {
s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
+ s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
}
/* TODO: We should also use TDR and RDR bits */
fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
}
-static void imx_spi_reset(DeviceState *dev)
+static void imx_spi_common_reset(IMXSPIState *s)
{
- IMXSPIState *s = IMX_SPI(dev);
-
- DPRINTF("\n");
-
- memset(s->regs, 0, sizeof(s->regs));
+ int i;
- s->regs[ECSPI_STATREG] = 0x00000003;
+ for (i = 0; i < ARRAY_SIZE(s->regs); i++) {
+ switch (i) {
+ case ECSPI_CONREG:
+ /* CONREG is not updated on soft reset */
+ break;
+ case ECSPI_STATREG:
+ s->regs[i] = 0x00000003;
+ break;
+ default:
+ s->regs[i] = 0;
+ break;
+ }
+ }
imx_spi_rxfifo_reset(s);
imx_spi_txfifo_reset(s);
+ s->burst_length = 0;
+}
+
+static void imx_spi_soft_reset(IMXSPIState *s)
+{
+ int i;
+
+ imx_spi_common_reset(s);
+
imx_spi_update_irq(s);
- s->burst_length = 0;
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
+ qemu_set_irq(s->cs_lines[i], 1);
+ }
+}
+
+static void imx_spi_reset(DeviceState *dev)
+{
+ IMXSPIState *s = IMX_SPI(dev);
+
+ imx_spi_common_reset(s);
+ s->regs[ECSPI_CONREG] = 0;
}
static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
return 0;
}
- switch (index) {
- case ECSPI_RXDATA:
- if (!imx_spi_is_enabled(s)) {
- value = 0;
- } else if (fifo32_is_empty(&s->rx_fifo)) {
- /* value is undefined */
- value = 0xdeadbeef;
- } else {
- /* read from the RX FIFO */
- value = fifo32_pop(&s->rx_fifo);
- }
-
- break;
- case ECSPI_TXDATA:
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
- TYPE_IMX_SPI, __func__);
-
- /* Reading from TXDATA gives 0 */
-
- break;
- case ECSPI_MSGDATA:
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
- TYPE_IMX_SPI, __func__);
+ value = s->regs[index];
+
+ if (imx_spi_is_enabled(s)) {
+ switch (index) {
+ case ECSPI_RXDATA:
+ if (fifo32_is_empty(&s->rx_fifo)) {
+ /* value is undefined */
+ value = 0xdeadbeef;
+ } else {
+ /* read from the RX FIFO */
+ value = fifo32_pop(&s->rx_fifo);
+ }
+ break;
+ case ECSPI_TXDATA:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "[%s]%s: Trying to read from TX FIFO\n",
+ TYPE_IMX_SPI, __func__);
- /* Reading from MSGDATA gives 0 */
+ /* Reading from TXDATA gives 0 */
+ break;
+ case ECSPI_MSGDATA:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "[%s]%s: Trying to read from MSG FIFO\n",
+ TYPE_IMX_SPI, __func__);
+ /* Reading from MSGDATA gives 0 */
+ break;
+ default:
+ break;
+ }
- break;
- default:
- value = s->regs[index];
- break;
+ imx_spi_update_irq(s);
}
-
DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
- imx_spi_update_irq(s);
-
return (uint64_t)value;
}
IMXSPIState *s = opaque;
uint32_t index = offset >> 2;
uint32_t change_mask;
+ uint32_t burst;
if (index >= ECSPI_MAX) {
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
(uint32_t)value);
+ if (!imx_spi_is_enabled(s)) {
+ /* Block is disabled */
+ if (index != ECSPI_CONREG) {
+ /* Ignore access */
+ return;
+ }
+ }
+
change_mask = s->regs[index] ^ value;
switch (index) {
TYPE_IMX_SPI, __func__);
break;
case ECSPI_TXDATA:
- if (!imx_spi_is_enabled(s)) {
- /* Ignore writes if device is disabled */
- break;
- } else if (fifo32_is_full(&s->tx_fifo)) {
+ if (fifo32_is_full(&s->tx_fifo)) {
/* Ignore writes if queue is full */
break;
}
case ECSPI_CONREG:
s->regs[ECSPI_CONREG] = value;
+ burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+ if (burst % 8) {
+ qemu_log_mask(LOG_UNIMP,
+ "[%s]%s: burst length %d not supported: rounding up to next multiple of 8\n",
+ TYPE_IMX_SPI, __func__, burst);
+ }
+
if (!imx_spi_is_enabled(s)) {
- /* device is disabled, so this is a reset */
- imx_spi_reset(DEVICE(s));
+ /* device is disabled, so this is a soft reset */
+ imx_spi_soft_reset(s);
+
return;
}
/* We are in master mode */
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
qemu_set_irq(s->cs_lines[i],
i == imx_spi_selected_channel(s) ? 0 : 1);
}
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
- ssi_auto_connect_slaves(dev, s->cs_lines, s->bus);
-
- for (i = 0; i < 4; ++i) {
+ for (i = 0; i < ECSPI_NUM_CS; ++i) {
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
}
- s->burst_length = 0;
-
fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
}
projects / mirror_qemu.git / blobdiff