#include "i2c.h"
#include "net.h"
#include "boards.h"
+#include "exec-memory.h"
#define GPIO_A 0
#define GPIO_B 1
typedef struct gptm_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t config;
uint32_t mode[2];
uint32_t control;
gptm_update_irq(s);
}
-static uint32_t gptm_read(void *opaque, target_phys_addr_t offset)
+static uint64_t gptm_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
gptm_state *s = (gptm_state *)opaque;
}
}
-static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value)
+static void gptm_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
{
gptm_state *s = (gptm_state *)opaque;
uint32_t oldval;
gptm_update_irq(s);
}
-static CPUReadMemoryFunc * const gptm_readfn[] = {
- gptm_read,
- gptm_read,
- gptm_read
-};
-
-static CPUWriteMemoryFunc * const gptm_writefn[] = {
- gptm_write,
- gptm_write,
- gptm_write
+static const MemoryRegionOps gptm_ops = {
+ .read = gptm_read,
+ .write = gptm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_stellaris_gptm = {
static int stellaris_gptm_init(SysBusDevice *dev)
{
- int iomemtype;
gptm_state *s = FROM_SYSBUS(gptm_state, dev);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_out(&dev->qdev, &s->trigger, 1);
- iomemtype = cpu_register_io_memory(gptm_readfn,
- gptm_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &gptm_ops, s,
+ "gptm", 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
s->opaque[0] = s->opaque[1] = s;
s->timer[0] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[0]);
/* System controller. */
typedef struct {
+ MemoryRegion iomem;
uint32_t pborctl;
uint32_t ldopctl;
uint32_t int_status;
}
}
-static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
+static uint64_t ssys_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
ssys_state *s = (ssys_state *)opaque;
}
}
-static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value)
+static void ssys_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
{
ssys_state *s = (ssys_state *)opaque;
ssys_update(s);
}
-static CPUReadMemoryFunc * const ssys_readfn[] = {
- ssys_read,
- ssys_read,
- ssys_read
-};
-
-static CPUWriteMemoryFunc * const ssys_writefn[] = {
- ssys_write,
- ssys_write,
- ssys_write
+static const MemoryRegionOps ssys_ops = {
+ .read = ssys_read,
+ .write = ssys_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ssys_reset(void *opaque)
s->rcgc[0] = 1;
s->scgc[0] = 1;
s->dcgc[0] = 1;
+ ssys_calculate_system_clock(s);
}
static int stellaris_sys_post_load(void *opaque, int version_id)
stellaris_board_info * board,
uint8_t *macaddr)
{
- int iomemtype;
ssys_state *s;
s = (ssys_state *)g_malloc0(sizeof(ssys_state));
s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
- iomemtype = cpu_register_io_memory(ssys_readfn,
- ssys_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x00001000, iomemtype);
+ memory_region_init_io(&s->iomem, &ssys_ops, s, "ssys", 0x00001000);
+ memory_region_add_subregion(get_system_memory(), base, &s->iomem);
ssys_reset(s);
vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
return 0;
SysBusDevice busdev;
i2c_bus *bus;
qemu_irq irq;
+ MemoryRegion iomem;
uint32_t msa;
uint32_t mcs;
uint32_t mdr;
#define STELLARIS_I2C_MCS_IDLE 0x20
#define STELLARIS_I2C_MCS_BUSBSY 0x40
-static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset)
+static uint64_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
}
static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
stellaris_i2c_update(s);
}
-static CPUReadMemoryFunc * const stellaris_i2c_readfn[] = {
- stellaris_i2c_read,
- stellaris_i2c_read,
- stellaris_i2c_read
-};
-
-static CPUWriteMemoryFunc * const stellaris_i2c_writefn[] = {
- stellaris_i2c_write,
- stellaris_i2c_write,
- stellaris_i2c_write
+static const MemoryRegionOps stellaris_i2c_ops = {
+ .read = stellaris_i2c_read,
+ .write = stellaris_i2c_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_stellaris_i2c = {
{
stellaris_i2c_state *s = FROM_SYSBUS(stellaris_i2c_state, dev);
i2c_bus *bus;
- int iomemtype;
sysbus_init_irq(dev, &s->irq);
bus = i2c_init_bus(&dev->qdev, "i2c");
s->bus = bus;
- iomemtype = cpu_register_io_memory(stellaris_i2c_readfn,
- stellaris_i2c_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &stellaris_i2c_ops, s,
+ "i2c", 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
/* ??? For now we only implement the master interface. */
stellaris_i2c_reset(s);
vmstate_register(&dev->qdev, -1, &vmstate_stellaris_i2c, s);
typedef struct
{
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t actss;
uint32_t ris;
uint32_t im;
}
}
-static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset)
+static uint64_t stellaris_adc_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
}
static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
return;
case 0x04: /* SSCTL */
if (value != 6) {
- hw_error("ADC: Unimplemented sequence %x\n",
+ hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
value);
}
s->ssctl[n] = value;
stellaris_adc_update(s);
}
-static CPUReadMemoryFunc * const stellaris_adc_readfn[] = {
- stellaris_adc_read,
- stellaris_adc_read,
- stellaris_adc_read
-};
-
-static CPUWriteMemoryFunc * const stellaris_adc_writefn[] = {
- stellaris_adc_write,
- stellaris_adc_write,
- stellaris_adc_write
+static const MemoryRegionOps stellaris_adc_ops = {
+ .read = stellaris_adc_read,
+ .write = stellaris_adc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_stellaris_adc = {
static int stellaris_adc_init(SysBusDevice *dev)
{
stellaris_adc_state *s = FROM_SYSBUS(stellaris_adc_state, dev);
- int iomemtype;
int n;
for (n = 0; n < 4; n++) {
sysbus_init_irq(dev, &s->irq[n]);
}
- iomemtype = cpu_register_io_memory(stellaris_adc_readfn,
- stellaris_adc_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &stellaris_adc_ops, s,
+ "adc", 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
stellaris_adc_reset(s);
qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1);
vmstate_register(&dev->qdev, -1, &vmstate_stellaris_adc, s);
0x40024000, 0x40025000, 0x40026000};
static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
+ MemoryRegion *address_space_mem = get_system_memory();
qemu_irq *pic;
DeviceState *gpio_dev[7];
qemu_irq gpio_in[7][8];
flash_size = ((board->dc0 & 0xffff) + 1) << 1;
sram_size = (board->dc0 >> 18) + 1;
- pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model);
+ pic = armv7m_init(address_space_mem,
+ flash_size, sram_size, kernel_filename, cpu_model);
if (board->dc1 & (1 << 16)) {
dev = sysbus_create_varargs("stellaris-adc", 0x40038000,
machine_init(stellaris_machine_init);
-static SSISlaveInfo stellaris_ssi_bus_info = {
- .qdev.name = "evb6965-ssi",
- .qdev.size = sizeof(stellaris_ssi_bus_state),
- .init = stellaris_ssi_bus_init,
- .transfer = stellaris_ssi_bus_transfer
+static void stellaris_ssi_bus_class_init(ObjectClass *klass, void *data)
+{
+ SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+
+ k->init = stellaris_ssi_bus_init;
+ k->transfer = stellaris_ssi_bus_transfer;
+}
+
+static TypeInfo stellaris_ssi_bus_info = {
+ .name = "evb6965-ssi",
+ .parent = TYPE_SSI_SLAVE,
+ .instance_size = sizeof(stellaris_ssi_bus_state),
+ .class_init = stellaris_ssi_bus_class_init,
+};
+
+static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = stellaris_i2c_init;
+}
+
+static TypeInfo stellaris_i2c_info = {
+ .name = "stellaris-i2c",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(stellaris_i2c_state),
+ .class_init = stellaris_i2c_class_init,
+};
+
+static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = stellaris_gptm_init;
+}
+
+static TypeInfo stellaris_gptm_info = {
+ .name = "stellaris-gptm",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(gptm_state),
+ .class_init = stellaris_gptm_class_init,
+};
+
+static void stellaris_adc_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = stellaris_adc_init;
+}
+
+static TypeInfo stellaris_adc_info = {
+ .name = "stellaris-adc",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(stellaris_adc_state),
+ .class_init = stellaris_adc_class_init,
};
-static void stellaris_register_devices(void)
+static void stellaris_register_types(void)
{
- sysbus_register_dev("stellaris-i2c", sizeof(stellaris_i2c_state),
- stellaris_i2c_init);
- sysbus_register_dev("stellaris-gptm", sizeof(gptm_state),
- stellaris_gptm_init);
- sysbus_register_dev("stellaris-adc", sizeof(stellaris_adc_state),
- stellaris_adc_init);
- ssi_register_slave(&stellaris_ssi_bus_info);
+ type_register_static(&stellaris_i2c_info);
+ type_register_static(&stellaris_gptm_info);
+ type_register_static(&stellaris_adc_info);
+ type_register_static(&stellaris_ssi_bus_info);
}
-device_init(stellaris_register_devices)
+type_init(stellaris_register_types)
projects / mirror_qemu.git / blobdiff