#include "loader.h"
#include "elf.h"
#include "blockdev.h"
+#include "exec-memory.h"
//#define DEBUG_IRQ
//#define DEBUG_EBUS
return kernel_size;
}
-void pic_info(Monitor *mon)
-{
-}
-
-void irq_info(Monitor *mon)
-{
-}
-
void cpu_check_irqs(CPUState *env)
{
uint32_t pil = env->pil_in |
}
/* EBUS (Eight bit bus) bridge */
-static void
+static ISABus *
pci_ebus_init(PCIBus *bus, int devfn)
{
qemu_irq *isa_irq;
+ PCIDevice *pci_dev;
+ ISABus *isa_bus;
- pci_create_simple(bus, devfn, "ebus");
+ pci_dev = pci_create_simple(bus, devfn, "ebus");
+ isa_bus = DO_UPCAST(ISABus, qbus,
+ qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
- isa_bus_irqs(isa_irq);
+ isa_bus_irqs(isa_bus, isa_irq);
+ return isa_bus;
}
static int
{
EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
- isa_bus_new(&pci_dev->qdev);
+ isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev));
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
pci_dev->config[0x05] = 0x00;
return 0;
}
-static PCIDeviceInfo ebus_info = {
- .qdev.name = "ebus",
- .qdev.size = sizeof(EbusState),
- .init = pci_ebus_init1,
- .vendor_id = PCI_VENDOR_ID_SUN,
- .device_id = PCI_DEVICE_ID_SUN_EBUS,
- .revision = 0x01,
- .class_id = PCI_CLASS_BRIDGE_OTHER,
-};
-
-static void pci_ebus_register(void)
+static void ebus_class_init(ObjectClass *klass, void *data)
{
- pci_qdev_register(&ebus_info);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->init = pci_ebus_init1;
+ k->vendor_id = PCI_VENDOR_ID_SUN;
+ k->device_id = PCI_DEVICE_ID_SUN_EBUS;
+ k->revision = 0x01;
+ k->class_id = PCI_CLASS_BRIDGE_OTHER;
}
-device_init(pci_ebus_register);
+static TypeInfo ebus_info = {
+ .name = "ebus",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(EbusState),
+ .class_init = ebus_class_init,
+};
+
+typedef struct PROMState {
+ SysBusDevice busdev;
+ MemoryRegion prom;
+} PROMState;
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
{
static int prom_init1(SysBusDevice *dev)
{
- ram_addr_t prom_offset;
+ PROMState *s = FROM_SYSBUS(PROMState, dev);
- prom_offset = qemu_ram_alloc(NULL, "sun4u.prom", PROM_SIZE_MAX);
- sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
+ memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
+ vmstate_register_ram_global(&s->prom);
+ memory_region_set_readonly(&s->prom, true);
+ sysbus_init_mmio(dev, &s->prom);
return 0;
}
-static SysBusDeviceInfo prom_info = {
- .init = prom_init1,
- .qdev.name = "openprom",
- .qdev.size = sizeof(SysBusDevice),
- .qdev.props = (Property[]) {
- {/* end of property list */}
- }
+static Property prom_properties[] = {
+ {/* end of property list */},
};
-static void prom_register_devices(void)
+static void prom_class_init(ObjectClass *klass, void *data)
{
- sysbus_register_withprop(&prom_info);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = prom_init1;
+ dc->props = prom_properties;
}
-device_init(prom_register_devices);
+static TypeInfo prom_info = {
+ .name = "openprom",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PROMState),
+ .class_init = prom_class_init,
+};
typedef struct RamDevice
{
SysBusDevice busdev;
+ MemoryRegion ram;
uint64_t size;
} RamDevice;
/* System RAM */
static int ram_init1(SysBusDevice *dev)
{
- ram_addr_t RAM_size, ram_offset;
RamDevice *d = FROM_SYSBUS(RamDevice, dev);
- RAM_size = d->size;
-
- ram_offset = qemu_ram_alloc(NULL, "sun4u.ram", RAM_size);
- sysbus_init_mmio(dev, RAM_size, ram_offset);
+ memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
+ vmstate_register_ram_global(&d->ram);
+ sysbus_init_mmio(dev, &d->ram);
return 0;
}
sysbus_mmio_map(s, 0, addr);
}
-static SysBusDeviceInfo ram_info = {
- .init = ram_init1,
- .qdev.name = "memory",
- .qdev.size = sizeof(RamDevice),
- .qdev.props = (Property[]) {
- DEFINE_PROP_UINT64("size", RamDevice, size, 0),
- DEFINE_PROP_END_OF_LIST(),
- }
+static Property ram_properties[] = {
+ DEFINE_PROP_UINT64("size", RamDevice, size, 0),
+ DEFINE_PROP_END_OF_LIST(),
};
-static void ram_register_devices(void)
+static void ram_class_init(ObjectClass *klass, void *data)
{
- sysbus_register_withprop(&ram_info);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = ram_init1;
+ dc->props = ram_properties;
}
-device_init(ram_register_devices);
+static TypeInfo ram_info = {
+ .name = "memory",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RamDevice),
+ .class_init = ram_class_init,
+};
static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
{
return env;
}
-static void sun4uv_init(ram_addr_t RAM_size,
+static void sun4uv_init(MemoryRegion *address_space_mem,
+ ram_addr_t RAM_size,
const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
unsigned int i;
long initrd_size, kernel_size;
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
+ ISABus *isa_bus;
qemu_irq *irq;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DriveInfo *fd[MAX_FD];
irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
&pci_bus3);
- isa_mem_base = APB_PCI_IO_BASE;
pci_vga_init(pci_bus);
// XXX Should be pci_bus3
- pci_ebus_init(pci_bus, -1);
+ isa_bus = pci_ebus_init(pci_bus, -1);
i = 0;
if (hwdef->console_serial_base) {
- serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
- serial_hds[i], 1, 1);
+ serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
+ NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
i++;
}
for(; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {
- serial_isa_init(i, serial_hds[i]);
+ serial_isa_init(isa_bus, i, serial_hds[i]);
}
}
for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
if (parallel_hds[i]) {
- parallel_init(i, parallel_hds[i]);
+ parallel_init(isa_bus, i, parallel_hds[i]);
}
}
pci_cmd646_ide_init(pci_bus, hd, 1);
- isa_create_simple("i8042");
+ isa_create_simple(isa_bus, "i8042");
for(i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
}
- fdctrl_init_isa(fd);
- nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
+ fdctrl_init_isa(isa_bus, fd);
+ nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
initrd_size = 0;
kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4uv_init(RAM_size, boot_devices, kernel_filename,
+ sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
}
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4uv_init(RAM_size, boot_devices, kernel_filename,
+ sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
}
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4uv_init(RAM_size, boot_devices, kernel_filename,
+ sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
}
.max_cpus = 1, // XXX for now
};
+static void sun4u_register_types(void)
+{
+ type_register_static(&ebus_info);
+ type_register_static(&prom_info);
+ type_register_static(&ram_info);
+}
+
static void sun4u_machine_init(void)
{
qemu_register_machine(&sun4u_machine);
qemu_register_machine(&niagara_machine);
}
+type_init(sun4u_register_types)
machine_init(sun4u_machine_init);
projects / mirror_qemu.git / blobdiff