* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "hw.h"
-#include "sun4m.h"
+
#include "console.h"
#include "pixel_ops.h"
+#include "sysbus.h"
+#include "qdev-addr.h"
#define MAXX 1024
#define MAXY 768
#define TCX_TEC_NREGS 0x1000
typedef struct TCXState {
+ SysBusDevice busdev;
target_phys_addr_t addr;
DisplayState *ds;
- QEMUConsole *console;
uint8_t *vram;
uint32_t *vram24, *cplane;
- ram_addr_t vram_offset, vram24_offset, cplane_offset;
- uint16_t width, height, depth;
- uint8_t r[256], g[256], b[256];
+ MemoryRegion vram_mem;
+ MemoryRegion vram_8bit;
+ MemoryRegion vram_24bit;
+ MemoryRegion vram_cplane;
+ MemoryRegion dac;
+ MemoryRegion tec;
+ MemoryRegion thc24;
+ MemoryRegion thc8;
+ ram_addr_t vram24_offset, cplane_offset;
+ uint32_t vram_size;
uint32_t palette[256];
+ uint8_t r[256], g[256], b[256];
+ uint16_t width, height, depth;
uint8_t dac_index, dac_state;
} TCXState;
static void tcx_screen_dump(void *opaque, const char *filename);
static void tcx24_screen_dump(void *opaque, const char *filename);
-static void tcx_invalidate_display(void *opaque);
-static void tcx24_invalidate_display(void *opaque);
+
+static void tcx_set_dirty(TCXState *s)
+{
+ memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
+}
+
+static void tcx24_set_dirty(TCXState *s)
+{
+ memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
+ memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
+}
static void update_palette_entries(TCXState *s, int start, int end)
{
int i;
for(i = start; i < end; i++) {
- switch(s->ds->depth) {
+ switch(ds_get_bits_per_pixel(s->ds)) {
default:
case 8:
s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
break;
case 15:
- if (s->ds->bgr)
- s->palette[i] = rgb_to_pixel15bgr(s->r[i], s->g[i], s->b[i]);
- else
- s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
+ s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
break;
case 16:
- if (s->ds->bgr)
- s->palette[i] = rgb_to_pixel16bgr(s->r[i], s->g[i], s->b[i]);
- else
- s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
+ s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
break;
case 32:
- if (s->ds->bgr)
+ if (is_surface_bgr(s->ds->surface))
s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
else
s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
break;
}
}
- if (s->depth == 24)
- tcx24_invalidate_display(s);
- else
- tcx_invalidate_display(s);
+ if (s->depth == 24) {
+ tcx24_set_dirty(s);
+ } else {
+ tcx_set_dirty(s);
+ }
}
static void tcx_draw_line32(TCXState *s1, uint8_t *d,
uint32_t *p = (uint32_t *)d;
uint32_t dval;
- bgr = s1->ds->bgr;
+ bgr = is_surface_bgr(s1->ds->surface);
for(x = 0; x < width; x++, s++, s24++) {
if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
// 24-bit direct, BGR order
p8++;
b = *p8++;
g = *p8++;
- r = *p8++;
+ r = *p8;
if (bgr)
dval = rgb_to_pixel32bgr(r, g, b);
else
}
}
-static inline int check_dirty(ram_addr_t page, ram_addr_t page24,
+static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24,
ram_addr_t cpage)
{
int ret;
unsigned int off;
- ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
+ ret = memory_region_get_dirty(&s->vram_mem, page, DIRTY_MEMORY_VGA);
for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
- ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
- ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
+ ret |= memory_region_get_dirty(&s->vram_mem, page24 + off,
+ DIRTY_MEMORY_VGA);
+ ret |= memory_region_get_dirty(&s->vram_mem, cpage + off,
+ DIRTY_MEMORY_VGA);
}
return ret;
}
ram_addr_t page_max, ram_addr_t page24,
ram_addr_t cpage)
{
- cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
- VGA_DIRTY_FLAG);
- page_min -= ts->vram_offset;
- page_max -= ts->vram_offset;
- cpu_physical_memory_reset_dirty(page24 + page_min * 4,
- page24 + page_max * 4 + TARGET_PAGE_SIZE,
- VGA_DIRTY_FLAG);
- cpu_physical_memory_reset_dirty(cpage + page_min * 4,
- cpage + page_max * 4 + TARGET_PAGE_SIZE,
- VGA_DIRTY_FLAG);
+ memory_region_reset_dirty(&ts->vram_mem,
+ page_min, page_max + TARGET_PAGE_SIZE,
+ DIRTY_MEMORY_VGA);
+ memory_region_reset_dirty(&ts->vram_mem,
+ page24 + page_min * 4,
+ page24 + page_max * 4 + TARGET_PAGE_SIZE,
+ DIRTY_MEMORY_VGA);
+ memory_region_reset_dirty(&ts->vram_mem,
+ cpage + page_min * 4,
+ cpage + page_max * 4 + TARGET_PAGE_SIZE,
+ DIRTY_MEMORY_VGA);
}
/* Fixed line length 1024 allows us to do nice tricks not possible on
uint8_t *d, *s;
void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
- if (ts->ds->depth == 0)
+ if (ds_get_bits_per_pixel(ts->ds) == 0)
return;
- page = ts->vram_offset;
+ page = 0;
y_start = -1;
- page_min = 0xffffffff;
+ page_min = -1;
page_max = 0;
- d = ts->ds->data;
+ d = ds_get_data(ts->ds);
s = ts->vram;
- dd = ts->ds->linesize;
+ dd = ds_get_linesize(ts->ds);
ds = 1024;
- switch (ts->ds->depth) {
+ switch (ds_get_bits_per_pixel(ts->ds)) {
case 32:
f = tcx_draw_line32;
break;
}
for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
- if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
+ if (memory_region_get_dirty(&ts->vram_mem, page, DIRTY_MEMORY_VGA)) {
if (y_start < 0)
y_start = y;
if (page < page_min)
ts->width, y - y_start);
}
/* reset modified pages */
- if (page_min <= page_max) {
- cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
- VGA_DIRTY_FLAG);
+ if (page_max >= page_min) {
+ memory_region_reset_dirty(&ts->vram_mem,
+ page_min, page_max + TARGET_PAGE_SIZE,
+ DIRTY_MEMORY_VGA);
}
}
uint8_t *d, *s;
uint32_t *cptr, *s24;
- if (ts->ds->depth != 32)
+ if (ds_get_bits_per_pixel(ts->ds) != 32)
return;
- page = ts->vram_offset;
+ page = 0;
page24 = ts->vram24_offset;
cpage = ts->cplane_offset;
y_start = -1;
- page_min = 0xffffffff;
+ page_min = -1;
page_max = 0;
- d = ts->ds->data;
+ d = ds_get_data(ts->ds);
s = ts->vram;
s24 = ts->vram24;
cptr = ts->cplane;
- dd = ts->ds->linesize;
+ dd = ds_get_linesize(ts->ds);
ds = 1024;
for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
- if (check_dirty(page, page24, cpage)) {
+ if (check_dirty(ts, page, page24, cpage)) {
if (y_start < 0)
y_start = y;
if (page < page_min)
ts->width, y - y_start);
}
/* reset modified pages */
- if (page_min <= page_max) {
+ if (page_max >= page_min) {
reset_dirty(ts, page_min, page_max, page24, cpage);
}
}
static void tcx_invalidate_display(void *opaque)
{
TCXState *s = opaque;
- int i;
- for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
- cpu_physical_memory_set_dirty(s->vram_offset + i);
- }
+ tcx_set_dirty(s);
+ qemu_console_resize(s->ds, s->width, s->height);
}
static void tcx24_invalidate_display(void *opaque)
{
TCXState *s = opaque;
- int i;
- tcx_invalidate_display(s);
- for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) {
- cpu_physical_memory_set_dirty(s->vram24_offset + i);
- cpu_physical_memory_set_dirty(s->cplane_offset + i);
- }
+ tcx_set_dirty(s);
+ tcx24_set_dirty(s);
+ qemu_console_resize(s->ds, s->width, s->height);
}
-static void tcx_save(QEMUFile *f, void *opaque)
+static int vmstate_tcx_post_load(void *opaque, int version_id)
{
TCXState *s = opaque;
- qemu_put_be16s(f, (uint16_t *)&s->height);
- qemu_put_be16s(f, (uint16_t *)&s->width);
- qemu_put_be16s(f, (uint16_t *)&s->depth);
- qemu_put_buffer(f, s->r, 256);
- qemu_put_buffer(f, s->g, 256);
- qemu_put_buffer(f, s->b, 256);
- qemu_put_8s(f, &s->dac_index);
- qemu_put_8s(f, &s->dac_state);
-}
-
-static int tcx_load(QEMUFile *f, void *opaque, int version_id)
-{
- TCXState *s = opaque;
- uint32_t dummy;
-
- if (version_id != 3 && version_id != 4)
- return -EINVAL;
-
- if (version_id == 3) {
- qemu_get_be32s(f, (uint32_t *)&dummy);
- qemu_get_be32s(f, (uint32_t *)&dummy);
- qemu_get_be32s(f, (uint32_t *)&dummy);
- }
- qemu_get_be16s(f, (uint16_t *)&s->height);
- qemu_get_be16s(f, (uint16_t *)&s->width);
- qemu_get_be16s(f, (uint16_t *)&s->depth);
- qemu_get_buffer(f, s->r, 256);
- qemu_get_buffer(f, s->g, 256);
- qemu_get_buffer(f, s->b, 256);
- qemu_get_8s(f, &s->dac_index);
- qemu_get_8s(f, &s->dac_state);
update_palette_entries(s, 0, 256);
- if (s->depth == 24)
- tcx24_invalidate_display(s);
- else
- tcx_invalidate_display(s);
+ if (s->depth == 24) {
+ tcx24_set_dirty(s);
+ } else {
+ tcx_set_dirty(s);
+ }
return 0;
}
-static void tcx_reset(void *opaque)
+static const VMStateDescription vmstate_tcx = {
+ .name ="tcx",
+ .version_id = 4,
+ .minimum_version_id = 4,
+ .minimum_version_id_old = 4,
+ .post_load = vmstate_tcx_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT16(height, TCXState),
+ VMSTATE_UINT16(width, TCXState),
+ VMSTATE_UINT16(depth, TCXState),
+ VMSTATE_BUFFER(r, TCXState),
+ VMSTATE_BUFFER(g, TCXState),
+ VMSTATE_BUFFER(b, TCXState),
+ VMSTATE_UINT8(dac_index, TCXState),
+ VMSTATE_UINT8(dac_state, TCXState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void tcx_reset(DeviceState *d)
{
- TCXState *s = opaque;
+ TCXState *s = container_of(d, TCXState, busdev.qdev);
/* Initialize palette */
memset(s->r, 0, 256);
s->r[255] = s->g[255] = s->b[255] = 255;
update_palette_entries(s, 0, 256);
memset(s->vram, 0, MAXX*MAXY);
- cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
- MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
+ memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
+ DIRTY_MEMORY_VGA);
s->dac_index = 0;
s->dac_state = 0;
}
-static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
return 0;
}
-static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
+ unsigned size)
{
TCXState *s = opaque;
- uint32_t saddr;
- saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
- switch (saddr) {
+ switch (addr) {
case 0:
s->dac_index = val >> 24;
s->dac_state = 0;
break;
- case 1:
+ case 4:
switch (s->dac_state) {
case 0:
s->r[s->dac_index] = val >> 24;
return;
}
-static CPUReadMemoryFunc *tcx_dac_read[3] = {
- NULL,
- NULL,
- tcx_dac_readl,
-};
-
-static CPUWriteMemoryFunc *tcx_dac_write[3] = {
- NULL,
- NULL,
- tcx_dac_writel,
+static const MemoryRegionOps tcx_dac_ops = {
+ .read = tcx_dac_readl,
+ .write = tcx_dac_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
return 0;
}
-static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void dummy_writel(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
}
-static CPUReadMemoryFunc *tcx_dummy_read[3] = {
- NULL,
- NULL,
- tcx_dummy_readl,
+static const MemoryRegionOps dummy_ops = {
+ .read = dummy_readl,
+ .write = dummy_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
- NULL,
- NULL,
- tcx_dummy_writel,
-};
-
-void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
- unsigned long vram_offset, int vram_size, int width, int height,
- int depth)
+static int tcx_init1(SysBusDevice *dev)
{
- TCXState *s;
- int io_memory, dummy_memory;
+ TCXState *s = FROM_SYSBUS(TCXState, dev);
+ ram_addr_t vram_offset = 0;
int size;
+ uint8_t *vram_base;
- s = qemu_mallocz(sizeof(TCXState));
- if (!s)
- return;
- s->ds = ds;
- s->addr = addr;
- s->vram_offset = vram_offset;
- s->width = width;
- s->height = height;
- s->depth = depth;
-
- // 8-bit plane
+ memory_region_init_ram(&s->vram_mem, "tcx.vram",
+ s->vram_size * (1 + 4 + 4));
+ vmstate_register_ram_global(&s->vram_mem);
+ vram_base = memory_region_get_ram_ptr(&s->vram_mem);
+
+ /* 8-bit plane */
s->vram = vram_base;
- size = vram_size;
- cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
+ size = s->vram_size;
+ memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
+ &s->vram_mem, vram_offset, size);
+ sysbus_init_mmio(dev, &s->vram_8bit);
vram_offset += size;
vram_base += size;
- io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
- cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS,
- io_memory);
-
- dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
- s);
- cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
- dummy_memory);
- if (depth == 24) {
- // 24-bit plane
- size = vram_size * 4;
+ /* DAC */
+ memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
+ sysbus_init_mmio(dev, &s->dac);
+
+ /* TEC (dummy) */
+ memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
+ sysbus_init_mmio(dev, &s->tec);
+ /* THC: NetBSD writes here even with 8-bit display: dummy */
+ memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
+ TCX_THC_NREGS_24);
+ sysbus_init_mmio(dev, &s->thc24);
+
+ if (s->depth == 24) {
+ /* 24-bit plane */
+ size = s->vram_size * 4;
s->vram24 = (uint32_t *)vram_base;
s->vram24_offset = vram_offset;
- cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
+ memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
+ &s->vram_mem, vram_offset, size);
+ sysbus_init_mmio(dev, &s->vram_24bit);
vram_offset += size;
vram_base += size;
- // Control plane
- size = vram_size * 4;
+ /* Control plane */
+ size = s->vram_size * 4;
s->cplane = (uint32_t *)vram_base;
s->cplane_offset = vram_offset;
- cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
- s->console = graphic_console_init(s->ds, tcx24_update_display,
- tcx24_invalidate_display,
- tcx24_screen_dump, NULL, s);
+ memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
+ &s->vram_mem, vram_offset, size);
+ sysbus_init_mmio(dev, &s->vram_cplane);
+
+ s->ds = graphic_console_init(tcx24_update_display,
+ tcx24_invalidate_display,
+ tcx24_screen_dump, NULL, s);
} else {
- cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
- dummy_memory);
- s->console = graphic_console_init(s->ds, tcx_update_display,
- tcx_invalidate_display,
- tcx_screen_dump, NULL, s);
+ /* THC 8 bit (dummy) */
+ memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
+ TCX_THC_NREGS_8);
+ sysbus_init_mmio(dev, &s->thc8);
+
+ s->ds = graphic_console_init(tcx_update_display,
+ tcx_invalidate_display,
+ tcx_screen_dump, NULL, s);
}
- // NetBSD writes here even with 8-bit display
- cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
- dummy_memory);
-
- register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
- qemu_register_reset(tcx_reset, s);
- tcx_reset(s);
- qemu_console_resize(s->console, width, height);
+
+ qemu_console_resize(s->ds, s->width, s->height);
+ return 0;
}
static void tcx_screen_dump(void *opaque, const char *filename)
fclose(f);
return;
}
+
+static Property tcx_properties[] = {
+ DEFINE_PROP_TADDR("addr", TCXState, addr, -1),
+ DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
+ DEFINE_PROP_UINT16("width", TCXState, width, -1),
+ DEFINE_PROP_UINT16("height", TCXState, height, -1),
+ DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void tcx_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = tcx_init1;
+}
+
+static DeviceInfo tcx_info = {
+ .name = "SUNW,tcx",
+ .size = sizeof(TCXState),
+ .reset = tcx_reset,
+ .vmsd = &vmstate_tcx,
+ .props = tcx_properties,
+ .class_init = tcx_class_init,
+};
+
+static void tcx_register_devices(void)
+{
+ sysbus_register_withprop(&tcx_info);
+}
+
+device_init(tcx_register_devices)
projects / mirror_qemu.git / blobdiff