#include "hw/irq.h"
#include "hw/ptimer.h"
#include "hw/qdev-properties.h"
-#include "qemu/main-loop.h"
#include "qemu/module.h"
#include "qemu/log.h"
+#include "qom/object.h"
/* Common timer implementation. */
}
}
-/* Reset the timer limit after settings have changed. */
+/*
+ * Reset the timer limit after settings have changed.
+ * May only be called from inside a ptimer transaction block.
+ */
static void arm_timer_recalibrate(arm_timer_state *s, int reload)
{
uint32_t limit;
switch (offset >> 2) {
case 0: /* TimerLoad */
s->limit = value;
+ ptimer_transaction_begin(s->timer);
arm_timer_recalibrate(s, 1);
+ ptimer_transaction_commit(s->timer);
break;
case 1: /* TimerValue */
/* ??? Linux seems to want to write to this readonly register.
Ignore it. */
break;
case 2: /* TimerControl */
+ ptimer_transaction_begin(s->timer);
if (s->control & TIMER_CTRL_ENABLE) {
/* Pause the timer if it is running. This may cause some
inaccuracy dure to rounding, but avoids a whole lot of other
/* Restart the timer if still enabled. */
ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
}
+ ptimer_transaction_commit(s->timer);
break;
case 3: /* TimerIntClr */
s->int_level = 0;
break;
case 6: /* TimerBGLoad */
s->limit = value;
+ ptimer_transaction_begin(s->timer);
arm_timer_recalibrate(s, 0);
+ ptimer_transaction_commit(s->timer);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
static arm_timer_state *arm_timer_init(uint32_t freq)
{
arm_timer_state *s;
- QEMUBH *bh;
s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
s->freq = freq;
s->control = TIMER_CTRL_IE;
- bh = qemu_bh_new(arm_timer_tick, s);
- s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
- vmstate_register(NULL, -1, &vmstate_arm_timer, s);
+ s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_DEFAULT);
+ vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s);
return s;
}
*/
#define TYPE_SP804 "sp804"
-#define SP804(obj) OBJECT_CHECK(SP804State, (obj), TYPE_SP804)
+OBJECT_DECLARE_SIMPLE_TYPE(SP804State, SP804)
-typedef struct SP804State {
+struct SP804State {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t freq0, freq1;
int level[2];
qemu_irq irq;
-} SP804State;
+};
static const uint8_t sp804_ids[] = {
/* Timer ID */
/* Integrator/CP timer module. */
#define TYPE_INTEGRATOR_PIT "integrator_pit"
-#define INTEGRATOR_PIT(obj) \
- OBJECT_CHECK(icp_pit_state, (obj), TYPE_INTEGRATOR_PIT)
+OBJECT_DECLARE_SIMPLE_TYPE(icp_pit_state, INTEGRATOR_PIT)
-typedef struct {
+struct icp_pit_state {
SysBusDevice parent_obj;
MemoryRegion iomem;
arm_timer_state *timer[3];
-} icp_pit_state;
+};
static uint64_t icp_pit_read(void *opaque, hwaddr offset,
unsigned size)
DeviceClass *k = DEVICE_CLASS(klass);
k->realize = sp804_realize;
- k->props = sp804_properties;
+ device_class_set_props(k, sp804_properties);
k->vmsd = &vmstate_sp804;
}