#include "sysemu/sysemu.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
#define OSMR0 0x00
#define OSMR1 0x04
uint64_t new_qemu;
now_vm = s->clock +
- muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());
+ muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);
for (i = 0; i < 4; i ++) {
new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
- get_ticks_per_sec(), s->freq);
+ NANOSECONDS_PER_SECOND, s->freq);
timer_mod(s->timer[i].qtimer, new_qemu);
}
}
now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
s->tm4[counter].lastload,
- s->tm4[counter].freq, get_ticks_per_sec());
+ s->tm4[counter].freq, NANOSECONDS_PER_SECOND);
new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
- get_ticks_per_sec(), s->tm4[counter].freq);
+ NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
timer_mod(s->tm4[n].tm.qtimer, new_qemu);
}
return s->tm4[tm].tm.value;
case OSCR:
return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
- s->lastload, s->freq, get_ticks_per_sec());
+ s->lastload, s->freq, NANOSECONDS_PER_SECOND);
case OSCR11: tm ++;
/* fall through */
case OSCR10: tm ++;
s->snapshot = s->tm4[tm - 1].clock + muldiv64(
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
s->tm4[tm - 1].lastload,
- s->tm4[tm - 1].freq, get_ticks_per_sec());
+ s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
else
s->snapshot = s->tm4[tm - 1].clock;
}
if (!s->tm4[tm].freq)
return s->tm4[tm].clock;
- return s->tm4[tm].clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
- s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
+ return s->tm4[tm].clock +
+ muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
+ s->tm4[tm].lastload, s->tm4[tm].freq,
+ NANOSECONDS_PER_SECOND);
case OIER:
return s->irq_enabled;
case OSSR: /* Status register */
case OSNR:
return s->snapshot;
default:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: unknown register 0x%02" HWADDR_PRIx "\n",
+ __func__, offset);
+ break;
badreg:
- hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
+ __func__, offset);
}
return 0;
}
break;
default:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: unknown register 0x%02" HWADDR_PRIx " "
+ "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
+ break;
badreg:
- hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: incorrect register 0x%02" HWADDR_PRIx " "
+ "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
}
}
if (t->num == 3)
if (i->reset3 & 1) {
i->reset3 = 0;
- qemu_system_reset_request();
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}