* Copyright (c) 2005-2007 CodeSourcery.
* Written by Paul Brook
*
- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.
*/
#include "sysbus.h"
#include "usb-ohci.h"
#include "boards.h"
#include "blockdev.h"
+#include "exec-memory.h"
/* Primary interrupt controller. */
typedef struct vpb_sic_state
{
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t level;
uint32_t mask;
uint32_t pic_enable;
int irq;
} vpb_sic_state;
+static const VMStateDescription vmstate_vpb_sic = {
+ .name = "versatilepb_sic",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(level, vpb_sic_state),
+ VMSTATE_UINT32(mask, vpb_sic_state),
+ VMSTATE_UINT32(pic_enable, vpb_sic_state),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void vpb_sic_update(vpb_sic_state *s)
{
uint32_t flags;
vpb_sic_update(s);
}
-static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
+static uint64_t vpb_sic_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
}
static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
vpb_sic_update(s);
}
-static CPUReadMemoryFunc * const vpb_sic_readfn[] = {
- vpb_sic_read,
- vpb_sic_read,
- vpb_sic_read
-};
-
-static CPUWriteMemoryFunc * const vpb_sic_writefn[] = {
- vpb_sic_write,
- vpb_sic_write,
- vpb_sic_write
+static const MemoryRegionOps vpb_sic_ops = {
+ .read = vpb_sic_read,
+ .write = vpb_sic_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int vpb_sic_init(SysBusDevice *dev)
{
vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
- int iomemtype;
int i;
qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
sysbus_init_irq(dev, &s->parent[i]);
}
s->irq = 31;
- iomemtype = cpu_register_io_memory(vpb_sic_readfn,
- vpb_sic_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
- /* ??? Save/restore. */
+ memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
return 0;
}
int board_id)
{
CPUState *env;
- ram_addr_t ram_offset;
+ MemoryRegion *sysmem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
qemu_irq *cpu_pic;
qemu_irq pic[32];
qemu_irq sic[32];
- DeviceState *dev;
+ DeviceState *dev, *sysctl;
+ SysBusDevice *busdev;
+ DeviceState *pl041;
PCIBus *pci_bus;
NICInfo *nd;
int n;
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- ram_offset = qemu_ram_alloc(NULL, "versatile.ram", ram_size);
+ memory_region_init_ram(ram, NULL, "versatile.ram", ram_size);
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero. */
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_add_subregion(sysmem, 0, ram);
+
+ sysctl = qdev_create(NULL, "realview_sysctl");
+ qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
+ qdev_init_nofail(sysctl);
+ qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
+ sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
- arm_sysctl_init(0x10000000, 0x41007004, 0x02000000);
cpu_pic = arm_pic_init_cpu(env);
dev = sysbus_create_varargs("pl190", 0x10140000,
cpu_pic[0], cpu_pic[1], NULL);
sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
- dev = sysbus_create_varargs("versatile_pci", 0x40000000,
- sic[27], sic[28], sic[29], sic[30], NULL);
+ dev = qdev_create(NULL, "versatile_pci");
+ busdev = sysbus_from_qdev(dev);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
+ sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
+ sysbus_connect_irq(busdev, 0, sic[27]);
+ sysbus_connect_irq(busdev, 1, sic[28]);
+ sysbus_connect_irq(busdev, 2, sic[29]);
+ sysbus_connect_irq(busdev, 3, sic[30]);
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
/* The Versatile PCI bridge does not provide access to PCI IO space,
for(n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
- if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) {
+ if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
smc91c111_init(nd, 0x10010000, sic[25]);
done_smc = 1;
} else {
/* The versatile/PB actually has a modified Color LCD controller
that includes hardware cursor support from the PL111. */
- sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
+ dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
+ /* Wire up the mux control signals from the SYS_CLCD register */
+ qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
/* Add PL031 Real Time Clock. */
sysbus_create_simple("pl031", 0x101e8000, pic[10]);
+ /* Add PL041 AACI Interface to the LM4549 codec */
+ pl041 = qdev_create(NULL, "pl041");
+ qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
+ qdev_init_nofail(pl041);
+ sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
+ sysbus_connect_irq(sysbus_from_qdev(pl041), 0, sic[24]);
+
/* Memory map for Versatile/PB: */
/* 0x10000000 System registers. */
/* 0x10001000 PCI controller config registers. */
machine_init(versatile_machine_init);
+static SysBusDeviceInfo vpb_sic_info = {
+ .init = vpb_sic_init,
+ .qdev.name = "versatilepb_sic",
+ .qdev.size = sizeof(vpb_sic_state),
+ .qdev.vmsd = &vmstate_vpb_sic,
+ .qdev.no_user = 1,
+};
+
static void versatilepb_register_devices(void)
{
- sysbus_register_dev("versatilepb_sic", sizeof(vpb_sic_state),
- vpb_sic_init);
+ sysbus_register_withprop(&vpb_sic_info);
}
device_init(versatilepb_register_devices)