/*
- * QEMU VGA Emulator. An S3 86c968 is emulated
+ * QEMU VGA Emulator.
*
* Copyright (c) 2003 Fabrice Bellard
*
#include "vl.h"
-#define NO_THUNK_TYPE_SIZE
-#include "thunk.h"
-
//#define DEBUG_VGA
//#define DEBUG_VGA_MEM
+//#define DEBUG_VGA_REG
+
+//#define DEBUG_S3
+//#define DEBUG_BOCHS_VBE
+
+#define CONFIG_S3VGA
#define MSR_COLOR_EMULATION 0x01
#define MSR_PAGE_SELECT 0x20
#define ST01_V_RETRACE 0x08
#define ST01_DISP_ENABLE 0x01
+/* bochs VBE support */
+#define CONFIG_BOCHS_VBE
+
+#define VBE_DISPI_MAX_XRES 1024
+#define VBE_DISPI_MAX_YRES 768
+
+#define VBE_DISPI_INDEX_ID 0x0
+#define VBE_DISPI_INDEX_XRES 0x1
+#define VBE_DISPI_INDEX_YRES 0x2
+#define VBE_DISPI_INDEX_BPP 0x3
+#define VBE_DISPI_INDEX_ENABLE 0x4
+#define VBE_DISPI_INDEX_BANK 0x5
+#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
+#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
+#define VBE_DISPI_INDEX_X_OFFSET 0x8
+#define VBE_DISPI_INDEX_Y_OFFSET 0x9
+#define VBE_DISPI_INDEX_NB 0xa
+
+#define VBE_DISPI_ID0 0xB0C0
+#define VBE_DISPI_ID1 0xB0C1
+#define VBE_DISPI_ID2 0xB0C2
+
+#define VBE_DISPI_DISABLED 0x00
+#define VBE_DISPI_ENABLED 0x01
+#define VBE_DISPI_LFB_ENABLED 0x40
+#define VBE_DISPI_NOCLEARMEM 0x80
+
+#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
+
typedef struct VGAState {
uint8_t *vram_ptr;
unsigned long vram_offset;
uint8_t dac_write_index;
uint8_t dac_cache[3]; /* used when writing */
uint8_t palette[768];
-
+ uint32_t bank_offset;
+#ifdef CONFIG_BOCHS_VBE
+ uint16_t vbe_index;
+ uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
+ uint32_t vbe_start_addr;
+ uint32_t vbe_line_offset;
+ uint32_t vbe_bank_mask;
+#endif
/* display refresh support */
DisplayState *ds;
uint32_t font_offsets[2];
uint32_t cursor_offset;
unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned b);
/* tell for each page if it has been updated since the last time */
- uint8_t vram_updated[VGA_RAM_SIZE / 4096];
uint32_t last_palette[256];
#define CH_ATTR_SIZE (160 * 100)
uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
VGAState vga_state;
int vga_io_memory;
-static uint32_t vga_ioport_read(CPUX86State *env, uint32_t addr)
+static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
{
- VGAState *s = &vga_state;
+ VGAState *s = opaque;
int val, index;
/* check port range access depending on color/monochrome mode */
break;
case 0x3c5:
val = s->sr[s->sr_index];
+#ifdef DEBUG_VGA_REG
+ printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
+#endif
break;
case 0x3c7:
val = s->dac_state;
break;
case 0x3cf:
val = s->gr[s->gr_index];
+#ifdef DEBUG_VGA_REG
+ printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
+#endif
break;
case 0x3b4:
case 0x3d4:
case 0x3b5:
case 0x3d5:
val = s->cr[s->cr_index];
+#ifdef DEBUG_VGA_REG
+ printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
+#endif
+#ifdef DEBUG_S3
+ if (s->cr_index >= 0x20)
+ printf("S3: CR read index=0x%x val=0x%x\n",
+ s->cr_index, val);
+#endif
break;
case 0x3ba:
case 0x3da:
break;
}
}
-#ifdef DEBUG_VGA
+#if defined(DEBUG_VGA)
printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
#endif
return val;
}
-static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
+static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
- VGAState *s = &vga_state;
+ VGAState *s = opaque;
int index, v;
/* check port range access depending on color/monochrome mode */
s->sr_index = val & 7;
break;
case 0x3c5:
+#ifdef DEBUG_VGA_REG
+ printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
+#endif
s->sr[s->sr_index] = val & sr_mask[s->sr_index];
break;
case 0x3c7:
s->gr_index = val & 0x0f;
break;
case 0x3cf:
+#ifdef DEBUG_VGA_REG
+ printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
+#endif
s->gr[s->gr_index] = val & gr_mask[s->gr_index];
break;
case 0x3b4:
break;
case 0x3b5:
case 0x3d5:
+#ifdef DEBUG_VGA_REG
+ printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
+#endif
/* handle CR0-7 protection */
if ((s->cr[11] & 0x80) && s->cr_index <= 7) {
/* can always write bit 4 of CR7 */
s->cr[s->cr_index] = val;
break;
+#ifdef CONFIG_S3VGA
/* S3 registers */
case 0x2d:
case 0x2e:
v = val & 3;
s->cr[0x69] = (s->cr[69] & ~0x0c) | (v << 2);
break;
+#endif
default:
s->cr[s->cr_index] = val;
break;
}
+#ifdef DEBUG_S3
+ if (s->cr_index >= 0x20)
+ printf("S3: CR write index=0x%x val=0x%x\n",
+ s->cr_index, val);
+#endif
break;
case 0x3ba:
case 0x3da:
}
}
+#ifdef CONFIG_BOCHS_VBE
+static uint32_t vbe_ioport_read(void *opaque, uint32_t addr)
+{
+ VGAState *s = opaque;
+ uint32_t val;
+
+ addr &= 1;
+ if (addr == 0) {
+ val = s->vbe_index;
+ } else {
+ if (s->vbe_index <= VBE_DISPI_INDEX_NB)
+ val = s->vbe_regs[s->vbe_index];
+ else
+ val = 0;
+#ifdef DEBUG_BOCHS_VBE
+ printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
+#endif
+ }
+ return val;
+}
+
+static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ VGAState *s = opaque;
+
+ addr &= 1;
+ if (addr == 0) {
+ s->vbe_index = val;
+ } else if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
+#ifdef DEBUG_BOCHS_VBE
+ printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
+#endif
+ switch(s->vbe_index) {
+ case VBE_DISPI_INDEX_ID:
+ if (val == VBE_DISPI_ID0 ||
+ val == VBE_DISPI_ID1 ||
+ val == VBE_DISPI_ID2) {
+ s->vbe_regs[s->vbe_index] = val;
+ }
+ break;
+ case VBE_DISPI_INDEX_XRES:
+ if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
+ s->vbe_regs[s->vbe_index] = val;
+ }
+ break;
+ case VBE_DISPI_INDEX_YRES:
+ if (val <= VBE_DISPI_MAX_YRES) {
+ s->vbe_regs[s->vbe_index] = val;
+ }
+ break;
+ case VBE_DISPI_INDEX_BPP:
+ if (val == 0)
+ val = 8;
+ if (val == 4 || val == 8 || val == 15 ||
+ val == 16 || val == 24 || val == 32) {
+ s->vbe_regs[s->vbe_index] = val;
+ }
+ break;
+ case VBE_DISPI_INDEX_BANK:
+ val &= s->vbe_bank_mask;
+ s->vbe_regs[s->vbe_index] = val;
+ s->bank_offset = (val << 16) - 0xa0000;
+ break;
+ case VBE_DISPI_INDEX_ENABLE:
+ if (val & VBE_DISPI_ENABLED) {
+ int h, shift_control;
+
+ s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
+ s->vbe_regs[VBE_DISPI_INDEX_XRES];
+ s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
+ s->vbe_regs[VBE_DISPI_INDEX_YRES];
+ s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
+ s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
+
+ if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
+ s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
+ else
+ s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
+ ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
+ s->vbe_start_addr = 0;
+
+ /* clear the screen (should be done in BIOS) */
+ if (!(val & VBE_DISPI_NOCLEARMEM)) {
+ memset(s->vram_ptr, 0,
+ s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
+ }
+
+ /* we initialize the VGA graphic mode (should be done
+ in BIOS) */
+ s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
+ s->cr[0x17] |= 3; /* no CGA modes */
+ s->cr[0x13] = s->vbe_line_offset >> 3;
+ /* width */
+ s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
+ /* height */
+ h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
+ s->cr[0x12] = h;
+ s->cr[0x07] = (s->cr[0x07] & ~0x42) |
+ ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
+ /* line compare to 1023 */
+ s->cr[0x18] = 0xff;
+ s->cr[0x07] |= 0x10;
+ s->cr[0x09] |= 0x40;
+
+ if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
+ shift_control = 0;
+ s->sr[0x01] &= ~8; /* no double line */
+ } else {
+ shift_control = 2;
+ }
+ s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
+ s->cr[0x09] &= ~0x9f; /* no double scan */
+ s->vbe_regs[s->vbe_index] = val;
+ } else {
+ /* XXX: the bios should do that */
+ s->bank_offset = -0xa0000;
+ }
+ break;
+ case VBE_DISPI_INDEX_VIRT_WIDTH:
+ {
+ int w, h, line_offset;
+
+ if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
+ return;
+ w = val;
+ if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
+ line_offset = w >> 1;
+ else
+ line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
+ h = s->vram_size / line_offset;
+ /* XXX: support weird bochs semantics ? */
+ if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
+ return;
+ s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
+ s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
+ s->vbe_line_offset = line_offset;
+ }
+ break;
+ case VBE_DISPI_INDEX_X_OFFSET:
+ case VBE_DISPI_INDEX_Y_OFFSET:
+ {
+ int x;
+ s->vbe_regs[s->vbe_index] = val;
+ s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
+ x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
+ if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
+ s->vbe_start_addr += x >> 1;
+ else
+ s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
+ s->vbe_start_addr >>= 2;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+#endif
+
/* called for accesses between 0xa0000 and 0xc0000 */
static uint32_t vga_mem_readb(uint32_t addr)
{
addr -= 0xa0000;
break;
case 1:
- addr -= 0xa0000;
- if (addr >= 0x10000)
+ if (addr >= 0xb0000)
return 0xff;
+ addr += s->bank_offset;
break;
case 2:
addr -= 0xb0000;
default:
case 3:
addr -= 0xb8000;
+ if (addr >= 0x8000)
+ return 0xff;
break;
}
return v;
}
-
/* called for accesses between 0xa0000 and 0xc0000 */
-void vga_mem_writeb(uint32_t addr, uint32_t val)
+void vga_mem_writeb(uint32_t addr, uint32_t val, uint32_t vaddr)
{
VGAState *s = &vga_state;
int memory_map_mode, plane, write_mode, b, func_select;
addr -= 0xa0000;
break;
case 1:
- addr -= 0xa0000;
- if (addr >= 0x10000)
+ if (addr >= 0xb0000)
return;
+ addr += s->bank_offset;
break;
case 2:
addr -= 0xb0000;
default:
case 3:
addr -= 0xb8000;
+ if (addr >= 0x8000)
+ return;
break;
}
#ifdef DEBUG_VGA_MEM
printf("vga: chain4: [0x%x]\n", addr);
#endif
- s->vram_updated[addr >> 12] = 1;
+ cpu_physical_memory_set_dirty(s->vram_offset + addr);
}
} else if (s->gr[5] & 0x10) {
/* odd/even mode (aka text mode mapping) */
#ifdef DEBUG_VGA_MEM
printf("vga: odd/even: [0x%x]\n", addr);
#endif
- s->vram_updated[addr >> 12] = 1;
+ cpu_physical_memory_set_dirty(s->vram_offset + addr);
}
} else {
/* standard VGA latched access */
case 3:
/* rotate */
b = s->gr[3] & 7;
- val = ((val >> b) | (val << (8 - b)));
+ val = (val >> b) | (val << (8 - b));
bit_mask = s->gr[8] & val;
val = mask16[s->gr[0]];
printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
addr * 4, write_mask, val);
#endif
- s->vram_updated[addr >> 10] = 1;
+ cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
}
}
-void vga_mem_writew(uint32_t addr, uint32_t val)
+void vga_mem_writew(uint32_t addr, uint32_t val, uint32_t vaddr)
{
- vga_mem_writeb(addr, val & 0xff);
- vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
+ vga_mem_writeb(addr, val & 0xff, vaddr);
+ vga_mem_writeb(addr + 1, (val >> 8) & 0xff, vaddr);
}
-void vga_mem_writel(uint32_t addr, uint32_t val)
+void vga_mem_writel(uint32_t addr, uint32_t val, uint32_t vaddr)
{
- vga_mem_writeb(addr, val & 0xff);
- vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
- vga_mem_writeb(addr + 2, (val >> 16) & 0xff);
- vga_mem_writeb(addr + 3, (val >> 24) & 0xff);
+ vga_mem_writeb(addr, val & 0xff, vaddr);
+ vga_mem_writeb(addr + 1, (val >> 8) & 0xff, vaddr);
+ vga_mem_writeb(addr + 2, (val >> 16) & 0xff, vaddr);
+ vga_mem_writeb(addr + 3, (val >> 24) & 0xff, vaddr);
}
typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
uint32_t start_addr, line_offset, line_compare, v;
full_update = 0;
- /* compute line_offset in bytes */
- v = (s->cr[0x51] >> 4) & 3; /* S3 extension */
- if (v == 0)
- v = (s->cr[0x43] >> 2) & 1; /* S3 extension */
- line_offset = s->cr[0x13] | (v << 8);
- line_offset <<= 3;
-
- /* starting address */
- start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
- start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */
+#ifdef CONFIG_BOCHS_VBE
+ if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
+ line_offset = s->vbe_line_offset;
+ start_addr = s->vbe_start_addr;
+ } else
+#endif
+ {
+ /* compute line_offset in bytes */
+ line_offset = s->cr[0x13];
+#ifdef CONFIG_S3VGA
+ v = (s->cr[0x51] >> 4) & 3; /* S3 extension */
+ if (v == 0)
+ v = (s->cr[0x43] >> 2) & 1; /* S3 extension */
+ line_offset |= (v << 8);
+#endif
+ line_offset <<= 3;
+
+ /* starting address */
+ start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
+#ifdef CONFIG_S3VGA
+ start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */
+#endif
+ }
+
/* line compare */
line_compare = s->cr[0x18] |
((s->cr[0x07] & 0x10) << 4) |
VGA_DRAW_LINE8,
VGA_DRAW_LINE15,
VGA_DRAW_LINE16,
+ VGA_DRAW_LINE24,
VGA_DRAW_LINE32,
VGA_DRAW_LINE_NB,
};
vga_draw_line16_16,
vga_draw_line16_32,
+ vga_draw_line24_8,
+ vga_draw_line24_15,
+ vga_draw_line24_16,
+ vga_draw_line24_32,
+
vga_draw_line32_8,
vga_draw_line32_15,
vga_draw_line32_16,
v = VGA_DRAW_LINE2;
}
} else {
- full_update |= update_palette256(s);
- v = VGA_DRAW_LINE8D2;
+#ifdef CONFIG_BOCHS_VBE
+ if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
+ switch(s->vbe_regs[VBE_DISPI_INDEX_BPP]) {
+ default:
+ case 8:
+ full_update |= update_palette256(s);
+ v = VGA_DRAW_LINE8;
+ break;
+ case 15:
+ v = VGA_DRAW_LINE15;
+ break;
+ case 16:
+ v = VGA_DRAW_LINE16;
+ break;
+ case 24:
+ v = VGA_DRAW_LINE24;
+ break;
+ case 32:
+ v = VGA_DRAW_LINE32;
+ break;
+ }
+ } else
+#endif
+ {
+ full_update |= update_palette256(s);
+ v = VGA_DRAW_LINE8D2;
+ }
}
vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->ds->depth)];
if (!(s->cr[0x17] & 2)) {
addr = (addr & ~0x8000) | ((y1 & 2) << 14);
}
- page0 = addr >> 12;
- page1 = (addr + bwidth - 1) >> 12;
- update = full_update | s->vram_updated[page0] | s->vram_updated[page1];
- if ((page1 - page0) > 1) {
+ page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
+ page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
+ update = full_update | cpu_physical_memory_is_dirty(page0) |
+ cpu_physical_memory_is_dirty(page1);
+ if ((page1 - page0) > TARGET_PAGE_SIZE) {
/* if wide line, can use another page */
- update |= s->vram_updated[page0 + 1];
+ update |= cpu_physical_memory_is_dirty(page0 + TARGET_PAGE_SIZE);
}
if (update) {
if (y_start < 0)
}
/* reset modified pages */
if (page_max != -1) {
- memset(s->vram_updated + page_min, 0, page_max - page_min + 1);
+ cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE);
}
}
-/* draw text terminal (very limited, just for simple boot debug
- messages) */
-static int last_cursor_pos;
-
-void vga_draw_dumb(VGAState *s)
-{
- int c, i, cursor_pos, eol;
-
- cursor_pos = s->cr[0x0f] | (s->cr[0x0e] << 8);
- eol = 0;
- for(i = last_cursor_pos; i < cursor_pos; i++) {
- /* XXX: should use vga RAM */
- c = phys_ram_base[0xb8000 + (i) * 2];
- if (c >= ' ') {
- putchar(c);
- eol = 0;
- } else {
- if (!eol)
- putchar('\n');
- eol = 1;
- }
- }
- fflush(stdout);
- last_cursor_pos = cursor_pos;
-}
-
void vga_update_display(void)
{
VGAState *s = &vga_state;
int full_update, graphic_mode;
if (s->ds->depth == 0) {
- vga_draw_dumb(s);
- } else {
+ /* nothing to do */
+ } else {
full_update = 0;
graphic_mode = s->gr[6] & 1;
if (graphic_mode != s->graphic_mode) {
void vga_reset(VGAState *s)
{
memset(s, 0, sizeof(VGAState));
+#ifdef CONFIG_S3VGA
/* chip ID for 8c968 */
s->cr[0x2d] = 0x88;
s->cr[0x2e] = 0xb0;
s->cr[0x2f] = 0x01; /* XXX: check revision code */
s->cr[0x30] = 0xe1;
+#endif
s->graphic_mode = -1; /* force full update */
}
vga_mem_writel,
};
-int vga_init(DisplayState *ds, uint8_t *vga_ram_base,
- unsigned long vga_ram_offset, int vga_ram_size)
+int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
+ unsigned long vga_ram_offset, int vga_ram_size)
{
VGAState *s = &vga_state;
int i, j, v, b;
s->vram_size = vga_ram_size;
s->ds = ds;
- register_ioport_write(0x3c0, 16, vga_ioport_write, 1);
+ register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
- register_ioport_write(0x3b4, 2, vga_ioport_write, 1);
- register_ioport_write(0x3d4, 2, vga_ioport_write, 1);
- register_ioport_write(0x3ba, 1, vga_ioport_write, 1);
- register_ioport_write(0x3da, 1, vga_ioport_write, 1);
+ register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
+ register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
+ register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
+ register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
- register_ioport_read(0x3c0, 16, vga_ioport_read, 1);
+ register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
- register_ioport_read(0x3b4, 2, vga_ioport_read, 1);
- register_ioport_read(0x3d4, 2, vga_ioport_read, 1);
- register_ioport_read(0x3ba, 1, vga_ioport_read, 1);
- register_ioport_read(0x3da, 1, vga_ioport_read, 1);
+ register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
+ register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
+ register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
+ register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
+ s->bank_offset = -0xa0000;
+
+#ifdef CONFIG_BOCHS_VBE
+ s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
+ s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
+ register_ioport_read(0x1ce, 1, 2, vbe_ioport_read, s);
+ register_ioport_read(0x1cf, 1, 2, vbe_ioport_read, s);
+
+ register_ioport_write(0x1ce, 1, 2, vbe_ioport_write, s);
+ register_ioport_write(0x1cf, 1, 2, vbe_ioport_write, s);
+#endif
vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write);
- cpu_register_physical_memory(0xa0000, 0x20000, vga_io_memory);
+#if defined (TARGET_I386)
+ cpu_register_physical_memory(0x000a0000, 0x20000, vga_io_memory);
+#ifdef CONFIG_BOCHS_VBE
+ /* XXX: use optimized standard vga accesses */
+ cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
+ vga_ram_size, vga_ram_offset);
+#endif
+#elif defined (TARGET_PPC)
+ cpu_register_physical_memory(0xf00a0000, 0x20000, vga_io_memory);
+#endif
return 0;
}
projects / mirror_qemu.git / blobdiff