qemu_set_irq(s->irq, !!s->regs[R_IP]);
}
-static uint64_t enet_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
{
struct XilinxAXIEnet *s = opaque;
uint32_t r = 0;
return r;
}
-static void enet_write(void *opaque, target_phys_addr_t addr,
+static void enet_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct XilinxAXIEnet *s = opaque;
s->maddr[s->fmi & 3][addr & 1] = value;
break;
+ case R_IS:
+ s->regs[addr] &= ~value;
+ break;
+
case 0x8000 ... 0x83ff:
s->ext_mtable[addr - 0x8000] = value;
break;