struct xlx_ethlite
{
SysBusDevice busdev;
+ MemoryRegion mmio;
qemu_irq irq;
- VLANClientState *vc;
+ NICState *nic;
+ NICConf conf;
uint32_t c_tx_pingpong;
uint32_t c_rx_pingpong;
unsigned int txbuf;
unsigned int rxbuf;
- uint8_t macaddr[6];
uint32_t regs[R_MAX];
};
}
}
-static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t
+eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
{
struct xlx_ethlite *s = opaque;
uint32_t r = 0;
D(qemu_log("%s %x=%x\n", __func__, addr * 4, r));
break;
- /* Rx packet data is endian fixed at the way into the rx rams. This
- * speeds things up because the ethlite MAC does not have a len
- * register. That means the CPU will issue MMIO reads for the entire
- * 2k rx buffer even for small packets.
- */
default:
- r = s->regs[addr];
+ r = tswap32(s->regs[addr]);
break;
}
return r;
}
static void
-eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+eth_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val64, unsigned int size)
{
struct xlx_ethlite *s = opaque;
unsigned int base = 0;
+ uint32_t value = val64;
addr >>= 2;
switch (addr)
D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
- qemu_send_packet(s->vc,
+ qemu_send_packet(&s->nic->nc,
(void *) &s->regs[base],
s->regs[base + R_TX_LEN0]);
D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
- memcpy(&s->macaddr[0], &s->regs[base], 6);
+ memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
}
s->regs[addr] = value;
break;
- /* Packet data, make sure it stays BE. */
default:
- s->regs[addr] = cpu_to_be32(value);
+ s->regs[addr] = tswap32(value);
break;
}
}
-static CPUReadMemoryFunc * const eth_read[] = {
- NULL, NULL, ð_readl,
-};
-
-static CPUWriteMemoryFunc * const eth_write[] = {
- NULL, NULL, ð_writel,
+static const MemoryRegionOps eth_ops = {
+ .read = eth_read,
+ .write = eth_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
};
-static int eth_can_rx(VLANClientState *vc)
+static int eth_can_rx(VLANClientState *nc)
{
- struct xlx_ethlite *s = vc->opaque;
+ struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
int r;
r = !(s->regs[R_RX_CTRL0] & CTRL_S);
return r;
}
-static ssize_t eth_rx(VLANClientState *vc, const uint8_t *buf, size_t size)
+static ssize_t eth_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
{
- struct xlx_ethlite *s = vc->opaque;
+ struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
unsigned int rxbase = s->rxbuf * (0x800 / 4);
- int i;
/* DA filter. */
- if (!(buf[0] & 0x80) && memcmp(&s->macaddr[0], buf, 6))
+ if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
return size;
if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
D(qemu_log("%s %d rxbase=%x\n", __func__, size, rxbase));
memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
- /* Bring it into host endianess. */
- for (i = 0; i < ((size + 3) / 4); i++) {
- uint32_t d = s->regs[rxbase + R_RX_BUF0 + i];
- s->regs[rxbase + R_RX_BUF0 + i] = be32_to_cpu(d);
- }
-
s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
return size;
}
-static void eth_cleanup(VLANClientState *vc)
+static void eth_cleanup(VLANClientState *nc)
{
- struct xlx_ethlite *s = vc->opaque;
- qemu_free(s);
+ struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
+
+ s->nic = NULL;
}
+static NetClientInfo net_xilinx_ethlite_info = {
+ .type = NET_CLIENT_TYPE_NIC,
+ .size = sizeof(NICState),
+ .can_receive = eth_can_rx,
+ .receive = eth_rx,
+ .cleanup = eth_cleanup,
+};
+
static int xilinx_ethlite_init(SysBusDevice *dev)
{
struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev);
- int regs;
sysbus_init_irq(dev, &s->irq);
s->rxbuf = 0;
- regs = cpu_register_io_memory(eth_read, eth_write, s);
- sysbus_init_mmio(dev, R_MAX * 4, regs);
+ memory_region_init_io(&s->mmio, ð_ops, s, "xilinx-ethlite", R_MAX * 4);
+ sysbus_init_mmio(dev, &s->mmio);
- qdev_get_macaddr(&dev->qdev, s->macaddr);
- s->vc = qdev_get_vlan_client(&dev->qdev,
- eth_can_rx, eth_rx, NULL, eth_cleanup, s);
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
+ s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
+ object_get_typename(OBJECT(dev)), dev->qdev.id, s);
+ qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
return 0;
}
-static SysBusDeviceInfo xilinx_ethlite_info = {
- .init = xilinx_ethlite_init,
- .qdev.name = "xilinx,ethlite",
- .qdev.size = sizeof(struct xlx_ethlite),
- .qdev.props = (Property[]) {
- DEFINE_PROP_UINT32("txpingpong", struct xlx_ethlite, c_tx_pingpong, 1),
- DEFINE_PROP_UINT32("rxpingpong", struct xlx_ethlite, c_rx_pingpong, 1),
- DEFINE_PROP_END_OF_LIST(),
- }
+static Property xilinx_ethlite_properties[] = {
+ DEFINE_PROP_UINT32("txpingpong", struct xlx_ethlite, c_tx_pingpong, 1),
+ DEFINE_PROP_UINT32("rxpingpong", struct xlx_ethlite, c_rx_pingpong, 1),
+ DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xilinx_ethlite_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = xilinx_ethlite_init;
+ dc->props = xilinx_ethlite_properties;
+}
+
+static TypeInfo xilinx_ethlite_info = {
+ .name = "xilinx,ethlite",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(struct xlx_ethlite),
+ .class_init = xilinx_ethlite_class_init,
};
-static void xilinx_ethlite_register(void)
+static void xilinx_ethlite_register_types(void)
{
- sysbus_register_withprop(&xilinx_ethlite_info);
+ type_register_static(&xilinx_ethlite_info);
}
-device_init(xilinx_ethlite_register)
+type_init(xilinx_ethlite_register_types)
projects / mirror_qemu.git / blobdiff