xilinx_spips_update_ixr(s);
}
-static uint64_t xilinx_spips_read(void *opaque, target_phys_addr_t addr,
+static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
unsigned size)
{
XilinxSPIPS *s = opaque;
}
-static void xilinx_spips_write(void *opaque, target_phys_addr_t addr,
+static void xilinx_spips_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
int mask = ~0;
DB_PRINT("inited device model\n");
+ s->spi = ssi_create_bus(&dev->qdev, "spi");
+
+ ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi);
sysbus_init_irq(dev, &s->irq);
for (i = 0; i < NUM_CS_LINES; ++i) {
sysbus_init_irq(dev, &s->cs_lines[i]);
sysbus_init_mmio(dev, &s->iomem);
s->irqline = -1;
- s->spi = ssi_create_bus(&dev->qdev, "spi");
fifo8_create(&s->rx_fifo, RXFF_A);
fifo8_create(&s->tx_fifo, TXFF_A);