x86: add AMD Northbridge MSR definition

[mirror_ubuntu-artful-kernel.git] / include / asm-x86 / msr-index.h

diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h
index a02eb2991349a699c74635ef6c9cd2ee2b87cf0d..3ed97144c07bcba49fd2c8dcca698b6d3a3ccf8e 100644 (file)
--- a/include/asm-x86/msr-index.h
+++ b/include/asm-x86/msr-index.h
@@ -63,6 +63,13 @@
 #define MSR_IA32_LASTINTFROMIP         0x000001dd
 #define MSR_IA32_LASTINTTOIP           0x000001de
 
+/* DEBUGCTLMSR bits (others vary by model): */
+#define _DEBUGCTLMSR_LBR       0 /* last branch recording */
+#define _DEBUGCTLMSR_BTF       1 /* single-step on branches */
+
+#define DEBUGCTLMSR_LBR                (1UL << _DEBUGCTLMSR_LBR)
+#define DEBUGCTLMSR_BTF                (1UL << _DEBUGCTLMSR_BTF)
+
 #define MSR_IA32_MC0_CTL               0x00000400
 #define MSR_IA32_MC0_STATUS            0x00000401
 #define MSR_IA32_MC0_ADDR              0x00000402
@@ -73,8 +80,41 @@
 #define MSR_P6_EVNTSEL0                        0x00000186
 #define MSR_P6_EVNTSEL1                        0x00000187
 
-/* K7/K8 MSRs. Not complete. See the architecture manual for a more
+/* AMD64 MSRs. Not complete. See the architecture manual for a more
    complete list. */
+
+#define MSR_AMD64_NB_CFG               0xc001001f
+#define MSR_AMD64_IBSFETCHCTL          0xc0011030
+#define MSR_AMD64_IBSFETCHLINAD                0xc0011031
+#define MSR_AMD64_IBSFETCHPHYSAD       0xc0011032
+#define MSR_AMD64_IBSOPCTL             0xc0011033
+#define MSR_AMD64_IBSOPRIP             0xc0011034
+#define MSR_AMD64_IBSOPDATA            0xc0011035
+#define MSR_AMD64_IBSOPDATA2           0xc0011036
+#define MSR_AMD64_IBSOPDATA3           0xc0011037
+#define MSR_AMD64_IBSDCLINAD           0xc0011038
+#define MSR_AMD64_IBSDCPHYSAD          0xc0011039
+#define MSR_AMD64_IBSCTL               0xc001103a
+
+/* Fam 10h MSRs */
+#define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
+#define FAM10H_MMIO_CONF_ENABLE                (1<<0)
+#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
+#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
+#define FAM10H_MMIO_CONF_BASE_MASK     0xfffffff
+#define FAM10H_MMIO_CONF_BASE_SHIFT    20
+
+/* K8 MSRs */
+#define MSR_K8_TOP_MEM1                        0xc001001a
+#define MSR_K8_TOP_MEM2                        0xc001001d
+#define MSR_K8_SYSCFG                  0xc0010010
+#define MSR_K8_HWCR                    0xc0010015
+#define MSR_K8_ENABLE_C1E              0xc0010055
+#define K8_MTRRFIXRANGE_DRAM_ENABLE    0x00040000 /* MtrrFixDramEn bit    */
+#define K8_MTRRFIXRANGE_DRAM_MODIFY    0x00080000 /* MtrrFixDramModEn bit */
+#define K8_MTRR_RDMEM_WRMEM_MASK       0x18181818 /* Mask: RdMem|WrMem    */
+
+/* K7 MSRs */
 #define MSR_K7_EVNTSEL0                        0xc0010000
 #define MSR_K7_PERFCTR0                        0xc0010004
 #define MSR_K7_EVNTSEL1                        0xc0010001
@@ -83,20 +123,10 @@
 #define MSR_K7_PERFCTR2                        0xc0010006
 #define MSR_K7_EVNTSEL3                        0xc0010003
 #define MSR_K7_PERFCTR3                        0xc0010007
-#define MSR_K8_TOP_MEM1                        0xc001001a
 #define MSR_K7_CLK_CTL                 0xc001001b
-#define MSR_K8_TOP_MEM2                        0xc001001d
-#define MSR_K8_SYSCFG                  0xc0010010
-
-#define K8_MTRRFIXRANGE_DRAM_ENABLE    0x00040000 /* MtrrFixDramEn bit    */
-#define K8_MTRRFIXRANGE_DRAM_MODIFY    0x00080000 /* MtrrFixDramModEn bit */
-#define K8_MTRR_RDMEM_WRMEM_MASK       0x18181818 /* Mask: RdMem|WrMem    */
-
 #define MSR_K7_HWCR                    0xc0010015
-#define MSR_K8_HWCR                    0xc0010015
 #define MSR_K7_FID_VID_CTL             0xc0010041
 #define MSR_K7_FID_VID_STATUS          0xc0010042
-#define MSR_K8_ENABLE_C1E              0xc0010055
 
 /* K6 MSRs */
 #define MSR_K6_EFER                    0xc0000080