#define PT_PHDR 6
#define PT_LOPROC 0x70000000
#define PT_HIPROC 0x7fffffff
-#define PT_MIPS_REGINFO 0x70000000
-#define PT_MIPS_OPTIONS 0x70000001
+
+#define PT_MIPS_REGINFO 0x70000000
+#define PT_MIPS_RTPROC 0x70000001
+#define PT_MIPS_OPTIONS 0x70000002
+#define PT_MIPS_ABIFLAGS 0x70000003
/* Flags in the e_flags field of the header */
/* MIPS architecture level. */
#define EF_MIPS_ABI 0x0000f000
#define EF_MIPS_FP64 0x00000200
#define EF_MIPS_NAN2008 0x00000400
-#define EF_MIPS_ARCH 0xf0000000
+
+/* MIPS machine variant */
+#define EF_MIPS_MACH_NONE 0x00000000 /* A standard MIPS implementation */
+#define EF_MIPS_MACH_3900 0x00810000 /* Toshiba R3900 */
+#define EF_MIPS_MACH_4010 0x00820000 /* LSI R4010 */
+#define EF_MIPS_MACH_4100 0x00830000 /* NEC VR4100 */
+#define EF_MIPS_MACH_4650 0x00850000 /* MIPS R4650 */
+#define EF_MIPS_MACH_4120 0x00870000 /* NEC VR4120 */
+#define EF_MIPS_MACH_4111 0x00880000 /* NEC VR4111/VR4181 */
+#define EF_MIPS_MACH_SB1 0x008a0000 /* Broadcom SB-1 */
+#define EF_MIPS_MACH_OCTEON 0x008b0000 /* Cavium Networks Octeon */
+#define EF_MIPS_MACH_XLR 0x008c0000 /* RMI Xlr */
+#define EF_MIPS_MACH_OCTEON2 0x008d0000 /* Cavium Networks Octeon2 */
+#define EF_MIPS_MACH_OCTEON3 0x008e0000 /* Cavium Networks Octeon3 */
+#define EF_MIPS_MACH_5400 0x00910000 /* NEC VR5400 */
+#define EF_MIPS_MACH_5900 0x00920000 /* Toshiba/Sony R5900 */
+#define EF_MIPS_MACH_5500 0x00980000 /* NEC VR5500 */
+#define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra RM9000 */
+#define EF_MIPS_MACH_LS2E 0x00a00000 /* ST Microelectronics Loongson 2E */
+#define EF_MIPS_MACH_LS2F 0x00a10000 /* ST Microelectronics Loongson 2F */
+#define EF_MIPS_MACH_LS3A 0x00a20000 /* ST Microelectronics Loongson 3A */
+#define EF_MIPS_MACH 0x00ff0000 /* EF_MIPS_MACH_xxx selection mask */
+
+#define MIPS_ABI_FP_UNKNOWN (-1) /* Unknown FP ABI (internal) */
+
+#define MIPS_ABI_FP_ANY 0x0 /* FP ABI doesn't matter */
+#define MIPS_ABI_FP_DOUBLE 0x1 /* -mdouble-float */
+#define MIPS_ABI_FP_SINGLE 0x2 /* -msingle-float */
+#define MIPS_ABI_FP_SOFT 0x3 /* -msoft-float */
+#define MIPS_ABI_FP_OLD_64 0x4 /* -mips32r2 -mfp64 */
+#define MIPS_ABI_FP_XX 0x5 /* -mfpxx */
+#define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 */
+#define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spreg */
+
+typedef struct mips_elf_abiflags_v0 {
+ uint16_t version; /* Version of flags structure */
+ uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 */
+ uint8_t isa_rev; /* The revision of ISA: */
+ /* - 0 for MIPS V and below, */
+ /* - 1-n otherwise. */
+ uint8_t gpr_size; /* The size of general purpose registers */
+ uint8_t cpr1_size; /* The size of co-processor 1 registers */
+ uint8_t cpr2_size; /* The size of co-processor 2 registers */
+ uint8_t fp_abi; /* The floating-point ABI */
+ uint32_t isa_ext; /* Mask of processor-specific extensions */
+ uint32_t ases; /* Mask of ASEs used */
+ uint32_t flags1; /* Mask of general flags */
+ uint32_t flags2;
+} Mips_elf_abiflags_v0;
/* These constants define the different elf file types */
#define ET_NONE 0
#define EM_UNICORE32 110 /* UniCore32 */
+#define EM_RISCV 243 /* RISC-V */
+
+#define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */
+
/*
* This is an interim value that we will use until the committee comes
* up with a final number.
/* ARM-specific values for sh_flags */
#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */
#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined
- in the input to a link step */
+ in the input to a link step */
/* ARM-specific program header flags */
#define PF_ARM_SB 0x10000000 /* Segment contains the location
- addressed by the static base */
+ addressed by the static base */
/* ARM relocs. */
#define R_ARM_NONE 0 /* No reloc */
#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
#define R_X86_64_RELATIVE 8 /* Adjust by program base */
#define R_X86_64_GOTPCREL 9 /* 32 bit signed pc relative
- offset to GOT */
+ offset to GOT */
#define R_X86_64_32 10 /* Direct 32 bit zero extended */
#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
#define R_X86_64_16 12 /* Direct 16 bit zero extended */
#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */
#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */
#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch
- prediction. */
+ prediction. */
#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */
#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */
/* Additional section indeces. */
#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared
- symbols in ANSI C. */
+ symbols in ANSI C. */
#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */
/* Legal values for sh_type field of Elf32_Shdr. */
#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */
#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */
+/* RISC-V relocations. */
+#define R_RISCV_NONE 0
+#define R_RISCV_32 1
+#define R_RISCV_64 2
+#define R_RISCV_RELATIVE 3
+#define R_RISCV_COPY 4
+#define R_RISCV_JUMP_SLOT 5
+#define R_RISCV_TLS_DTPMOD32 6
+#define R_RISCV_TLS_DTPMOD64 7
+#define R_RISCV_TLS_DTPREL32 8
+#define R_RISCV_TLS_DTPREL64 9
+#define R_RISCV_TLS_TPREL32 10
+#define R_RISCV_TLS_TPREL64 11
+#define R_RISCV_BRANCH 16
+#define R_RISCV_JAL 17
+#define R_RISCV_CALL 18
+#define R_RISCV_CALL_PLT 19
+#define R_RISCV_GOT_HI20 20
+#define R_RISCV_TLS_GOT_HI20 21
+#define R_RISCV_TLS_GD_HI20 22
+#define R_RISCV_PCREL_HI20 23
+#define R_RISCV_PCREL_LO12_I 24
+#define R_RISCV_PCREL_LO12_S 25
+#define R_RISCV_HI20 26
+#define R_RISCV_LO12_I 27
+#define R_RISCV_LO12_S 28
+#define R_RISCV_TPREL_HI20 29
+#define R_RISCV_TPREL_LO12_I 30
+#define R_RISCV_TPREL_LO12_S 31
+#define R_RISCV_TPREL_ADD 32
+#define R_RISCV_ADD8 33
+#define R_RISCV_ADD16 34
+#define R_RISCV_ADD32 35
+#define R_RISCV_ADD64 36
+#define R_RISCV_SUB8 37
+#define R_RISCV_SUB16 38
+#define R_RISCV_SUB32 39
+#define R_RISCV_SUB64 40
+#define R_RISCV_GNU_VTINHERIT 41
+#define R_RISCV_GNU_VTENTRY 42
+#define R_RISCV_ALIGN 43
+#define R_RISCV_RVC_BRANCH 44
+#define R_RISCV_RVC_JUMP 45
+#define R_RISCV_RVC_LUI 46
+#define R_RISCV_GPREL_I 47
+#define R_RISCV_GPREL_S 48
+#define R_RISCV_TPREL_I 49
+#define R_RISCV_TPREL_S 50
+#define R_RISCV_RELAX 51
+#define R_RISCV_SUB6 52
+#define R_RISCV_SET6 53
+#define R_RISCV_SET8 54
+#define R_RISCV_SET16 55
+#define R_RISCV_SET32 56
+
+/* RISC-V ELF Flags. */
+#define EF_RISCV_RVC 0x0001
+#define EF_RISCV_FLOAT_ABI 0x0006
+#define EF_RISCV_FLOAT_ABI_SOFT 0x0000
+#define EF_RISCV_FLOAT_ABI_SINGLE 0x0002
+#define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004
+#define EF_RISCV_FLOAT_ABI_QUAD 0x0006
+#define EF_RISCV_RVE 0x0008
+#define EF_RISCV_TSO 0x0010
+
typedef struct elf32_rel {
Elf32_Addr r_offset;
Elf32_Word r_info;
#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */
#define ELFOSABI_MODESTO 11 /* Novell Modesto. */
#define ELFOSABI_OPENBSD 12 /* OpenBSD. */
+#define ELFOSABI_ARM_FDPIC 65 /* ARM FDPIC */
#define ELFOSABI_ARM 97 /* ARM */
#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */
#define NT_ARM_HW_WATCH 0x403 /* ARM hardware watchpoint registers */
#define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */
+/*
+ * Physical entry point into the kernel.
+ *
+ * 32bit entry point into the kernel. When requested to launch the
+ * guest kernel, use this entry point to launch the guest in 32-bit
+ * protected mode with paging disabled.
+ *
+ * [ Corresponding definition in Linux kernel: include/xen/interface/elfnote.h ]
+ */
+#define XEN_ELFNOTE_PHYS32_ENTRY 18 /* 0x12 */
/* Note header in a PT_NOTE section */
typedef struct elf32_note {
projects / mirror_qemu.git / blobdiff