* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef IOMMU_COMMON_H
-#define IOMMU_COMMON_H
+#ifndef HW_I386_X86_IOMMU_H
+#define HW_I386_X86_IOMMU_H
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
+#include "hw/pci/msi.h"
+#include "qom/object.h"
#define TYPE_X86_IOMMU_DEVICE ("x86-iommu")
-#define X86_IOMMU_DEVICE(obj) \
- OBJECT_CHECK(X86IOMMUState, (obj), TYPE_X86_IOMMU_DEVICE)
-#define X86_IOMMU_CLASS(klass) \
- OBJECT_CLASS_CHECK(X86IOMMUClass, (klass), TYPE_X86_IOMMU_DEVICE)
-#define X86_IOMMU_GET_CLASS(obj) \
- OBJECT_GET_CLASS(X86IOMMUClass, obj, TYPE_X86_IOMMU_DEVICE)
+OBJECT_DECLARE_TYPE(X86IOMMUState, X86IOMMUClass, X86_IOMMU_DEVICE)
#define X86_IOMMU_SID_INVALID (0xffff)
-typedef struct X86IOMMUState X86IOMMUState;
-typedef struct X86IOMMUClass X86IOMMUClass;
-
-typedef enum IommuType {
- TYPE_INTEL,
- TYPE_AMD,
- TYPE_NONE
-} IommuType;
+typedef struct X86IOMMUIrq X86IOMMUIrq;
+typedef struct X86IOMMU_MSIMessage X86IOMMU_MSIMessage;
struct X86IOMMUClass {
SysBusDeviceClass parent;
struct X86IOMMUState {
SysBusDevice busdev;
- bool intr_supported; /* Whether vIOMMU supports IR */
+ OnOffAuto intr_supported; /* Whether vIOMMU supports IR */
bool dt_supported; /* Whether vIOMMU supports DT */
bool pt_supported; /* Whether vIOMMU supports pass-through */
- IommuType type; /* IOMMU type - AMD/Intel */
QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */
};
+bool x86_iommu_ir_supported(X86IOMMUState *s);
+
+/* Generic IRQ entry information when interrupt remapping is enabled */
+struct X86IOMMUIrq {
+ /* Used by both IOAPIC/MSI interrupt remapping */
+ uint8_t trigger_mode;
+ uint8_t vector;
+ uint8_t delivery_mode;
+ uint32_t dest;
+ uint8_t dest_mode;
+
+ /* only used by MSI interrupt remapping */
+ uint8_t redir_hint;
+ uint8_t msi_addr_last_bits;
+};
+
+struct X86IOMMU_MSIMessage {
+ union {
+ struct {
+#if HOST_BIG_ENDIAN
+ uint32_t __addr_head:12; /* 0xfee */
+ uint32_t dest:8;
+ uint32_t __reserved:8;
+ uint32_t redir_hint:1;
+ uint32_t dest_mode:1;
+ uint32_t __not_used:2;
+#else
+ uint32_t __not_used:2;
+ uint32_t dest_mode:1;
+ uint32_t redir_hint:1;
+ uint32_t __reserved:8;
+ uint32_t dest:8;
+ uint32_t __addr_head:12; /* 0xfee */
+#endif
+ uint32_t __addr_hi;
+ } QEMU_PACKED;
+ uint64_t msi_addr;
+ };
+ union {
+ struct {
+#if HOST_BIG_ENDIAN
+ uint16_t trigger_mode:1;
+ uint16_t level:1;
+ uint16_t __resved:3;
+ uint16_t delivery_mode:3;
+ uint16_t vector:8;
+#else
+ uint16_t vector:8;
+ uint16_t delivery_mode:3;
+ uint16_t __resved:3;
+ uint16_t level:1;
+ uint16_t trigger_mode:1;
+#endif
+ uint16_t __resved1;
+ } QEMU_PACKED;
+ uint32_t msi_data;
+ };
+};
+
/**
* x86_iommu_get_default - get default IOMMU device
* @return: pointer to default IOMMU device
*/
X86IOMMUState *x86_iommu_get_default(void);
-/*
- * x86_iommu_get_type - get IOMMU type
- */
-IommuType x86_iommu_get_type(void);
-
/**
* x86_iommu_iec_register_notifier - register IEC (Interrupt Entry
* Cache) notifiers
void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global,
uint32_t index, uint32_t mask);
+/**
+ * x86_iommu_irq_to_msi_message - Populate one MSIMessage from X86IOMMUIrq
+ * @X86IOMMUIrq: The IRQ information
+ * @out: Output MSI message
+ */
+void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *out);
#endif