KVM: arm64: vgic-v3: Enable trapping of Group-0 system registers

[mirror_ubuntu-zesty-kernel.git] / include / linux / irqchip / arm-gic-v3.h

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index b7e34313cdfe4a68fee46334158d7d22111993e9..6c3406dc1187c6424fce41990014454972faff38 100644 (file)
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -239,7 +239,7 @@
 #define GITS_TYPER_PTA                 (1UL << 19)
 #define GITS_TYPER_HWCOLLCNT_SHIFT     24
 
-#define GITS_CBASER_VALID                      (1UL << 63)
+#define GITS_CBASER_VALID                      (1ULL << 63)
 #define GITS_CBASER_SHAREABILITY_SHIFT         (10)
 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT   (59)
 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT   (53)
@@ -265,7 +265,7 @@
 
 #define GITS_BASER_NR_REGS             8
 
-#define GITS_BASER_VALID                       (1UL << 63)
+#define GITS_BASER_VALID                       (1ULL << 63)
 #define GITS_BASER_INDIRECT                    (1ULL << 62)
 
 #define GITS_BASER_INNER_CACHEABILITY_SHIFT    (59)
@@ -295,10 +295,10 @@
 #define GITS_BASER_InnerShareable                                      \
        GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
 #define GITS_BASER_PAGE_SIZE_SHIFT     (8)
-#define GITS_BASER_PAGE_SIZE_4K                (0UL << GITS_BASER_PAGE_SIZE_SHIFT)
-#define GITS_BASER_PAGE_SIZE_16K       (1UL << GITS_BASER_PAGE_SIZE_SHIFT)
-#define GITS_BASER_PAGE_SIZE_64K       (2UL << GITS_BASER_PAGE_SIZE_SHIFT)
-#define GITS_BASER_PAGE_SIZE_MASK      (3UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_4K                (0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_16K       (1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_64K       (2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_MASK      (3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
 #define GITS_BASER_PAGES_MAX           256
 #define GITS_BASER_PAGES_SHIFT         (0)
 #define GITS_BASER_NR_PAGES(r)         (((r) & 0xff) + 1)
@@ -352,8 +352,30 @@
 /*
  * CPU interface registers
  */
-#define ICC_CTLR_EL1_EOImode_drop_dir  (0U << 1)
-#define ICC_CTLR_EL1_EOImode_drop      (1U << 1)
+#define ICC_CTLR_EL1_EOImode_SHIFT     (1)
+#define ICC_CTLR_EL1_EOImode_drop_dir  (0U << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_EOImode_drop      (1U << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_EOImode_MASK      (1 << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_CBPR_SHIFT                0
+#define ICC_CTLR_EL1_CBPR_MASK         (1 << ICC_CTLR_EL1_CBPR_SHIFT)
+#define ICC_CTLR_EL1_PRI_BITS_SHIFT    8
+#define ICC_CTLR_EL1_PRI_BITS_MASK     (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
+#define ICC_CTLR_EL1_ID_BITS_SHIFT     11
+#define ICC_CTLR_EL1_ID_BITS_MASK      (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
+#define ICC_CTLR_EL1_SEIS_SHIFT                14
+#define ICC_CTLR_EL1_SEIS_MASK         (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
+#define ICC_CTLR_EL1_A3V_SHIFT         15
+#define ICC_CTLR_EL1_A3V_MASK          (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
+#define ICC_PMR_EL1_SHIFT              0
+#define ICC_PMR_EL1_MASK               (0xff << ICC_PMR_EL1_SHIFT)
+#define ICC_BPR0_EL1_SHIFT             0
+#define ICC_BPR0_EL1_MASK              (0x7 << ICC_BPR0_EL1_SHIFT)
+#define ICC_BPR1_EL1_SHIFT             0
+#define ICC_BPR1_EL1_MASK              (0x7 << ICC_BPR1_EL1_SHIFT)
+#define ICC_IGRPEN0_EL1_SHIFT          0
+#define ICC_IGRPEN0_EL1_MASK           (1 << ICC_IGRPEN0_EL1_SHIFT)
+#define ICC_IGRPEN1_EL1_SHIFT          0
+#define ICC_IGRPEN1_EL1_MASK           (1 << ICC_IGRPEN1_EL1_SHIFT)
 #define ICC_SRE_EL1_SRE                        (1U << 0)
 
 /*
@@ -370,6 +392,7 @@
 #define ICH_LR_PHYS_ID_SHIFT           32
 #define ICH_LR_PHYS_ID_MASK            (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
 #define ICH_LR_PRIORITY_SHIFT          48
+#define ICH_LR_PRIORITY_MASK           (0xffULL << ICH_LR_PRIORITY_SHIFT)
 
 /* These are for GICv2 emulation only */
 #define GICH_LR_VIRTUALID              (0x3ffUL << 0)
@@ -381,15 +404,36 @@
 
 #define ICH_HCR_EN                     (1 << 0)
 #define ICH_HCR_UIE                    (1 << 1)
+#define ICH_HCR_TALL0                  (1 << 11)
+#define ICH_HCR_TALL1                  (1 << 12)
+#define ICH_HCR_EOIcount_SHIFT         27
+#define ICH_HCR_EOIcount_MASK          (0x1f << ICH_HCR_EOIcount_SHIFT)
 
 #define ICH_VMCR_CTLR_SHIFT            0
 #define ICH_VMCR_CTLR_MASK             (0x21f << ICH_VMCR_CTLR_SHIFT)
+#define ICH_VMCR_CBPR_SHIFT            4
+#define ICH_VMCR_CBPR_MASK             (1 << ICH_VMCR_CBPR_SHIFT)
+#define ICH_VMCR_EOIM_SHIFT            9
+#define ICH_VMCR_EOIM_MASK             (1 << ICH_VMCR_EOIM_SHIFT)
 #define ICH_VMCR_BPR1_SHIFT            18
 #define ICH_VMCR_BPR1_MASK             (7 << ICH_VMCR_BPR1_SHIFT)
 #define ICH_VMCR_BPR0_SHIFT            21
 #define ICH_VMCR_BPR0_MASK             (7 << ICH_VMCR_BPR0_SHIFT)
 #define ICH_VMCR_PMR_SHIFT             24
 #define ICH_VMCR_PMR_MASK              (0xffUL << ICH_VMCR_PMR_SHIFT)
+#define ICH_VMCR_ENG0_SHIFT            0
+#define ICH_VMCR_ENG0_MASK             (1 << ICH_VMCR_ENG0_SHIFT)
+#define ICH_VMCR_ENG1_SHIFT            1
+#define ICH_VMCR_ENG1_MASK             (1 << ICH_VMCR_ENG1_SHIFT)
+
+#define ICH_VTR_PRI_BITS_SHIFT         29
+#define ICH_VTR_PRI_BITS_MASK          (7 << ICH_VTR_PRI_BITS_SHIFT)
+#define ICH_VTR_ID_BITS_SHIFT          23
+#define ICH_VTR_ID_BITS_MASK           (7 << ICH_VTR_ID_BITS_SHIFT)
+#define ICH_VTR_SEIS_SHIFT             22
+#define ICH_VTR_SEIS_MASK              (1 << ICH_VTR_SEIS_SHIFT)
+#define ICH_VTR_A3V_SHIFT              21
+#define ICH_VTR_A3V_MASK               (1 << ICH_VTR_A3V_SHIFT)
 
 #define ICC_IAR1_EL1_SPURIOUS          0x3ff