net/mlx5: Expose resource dump register mapping

[mirror_ubuntu-hirsute-kernel.git] / include / linux / mlx5 / mlx5_ifc.h

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 5d54fccf87fc57484321db24111a80b5df2fcdaf..6fe0431e11ec4fe3c4bca01177b7871cf9e6558b 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -87,6 +87,7 @@ enum {
 enum {
        MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
        MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
+       MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
 };
 
 enum {
@@ -822,7 +823,9 @@ struct mlx5_ifc_qos_cap_bits {
 struct mlx5_ifc_debug_cap_bits {
        u8         core_dump_general[0x1];
        u8         core_dump_qp[0x1];
-       u8         reserved_at_2[0x1e];
+       u8         reserved_at_2[0x7];
+       u8         resource_dump[0x1];
+       u8         reserved_at_a[0x16];
 
        u8         reserved_at_20[0x2];
        u8         stall_detect[0x1];
@@ -953,6 +956,19 @@ struct mlx5_ifc_device_event_cap_bits {
        u8         user_unaffiliated_events[4][0x40];
 };
 
+struct mlx5_ifc_device_virtio_emulation_cap_bits {
+       u8         reserved_at_0[0x20];
+
+       u8         reserved_at_20[0x13];
+       u8         log_doorbell_stride[0x5];
+       u8         reserved_at_38[0x3];
+       u8         log_doorbell_bar_size[0x5];
+
+       u8         doorbell_bar_offset[0x40];
+
+       u8         reserved_at_80[0x780];
+};
+
 enum {
        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
@@ -1753,6 +1769,132 @@ struct mlx5_ifc_resize_field_select_bits {
        u8         resize_field_select[0x20];
 };
 
+struct mlx5_ifc_resource_dump_bits {
+       u8         more_dump[0x1];
+       u8         inline_dump[0x1];
+       u8         reserved_at_2[0xa];
+       u8         seq_num[0x4];
+       u8         segment_type[0x10];
+
+       u8         reserved_at_20[0x10];
+       u8         vhca_id[0x10];
+
+       u8         index1[0x20];
+
+       u8         index2[0x20];
+
+       u8         num_of_obj1[0x10];
+       u8         num_of_obj2[0x10];
+
+       u8         reserved_at_a0[0x20];
+
+       u8         device_opaque[0x40];
+
+       u8         mkey[0x20];
+
+       u8         size[0x20];
+
+       u8         address[0x40];
+
+       u8         inline_data[52][0x20];
+};
+
+struct mlx5_ifc_resource_dump_menu_record_bits {
+       u8         reserved_at_0[0x4];
+       u8         num_of_obj2_supports_active[0x1];
+       u8         num_of_obj2_supports_all[0x1];
+       u8         must_have_num_of_obj2[0x1];
+       u8         support_num_of_obj2[0x1];
+       u8         num_of_obj1_supports_active[0x1];
+       u8         num_of_obj1_supports_all[0x1];
+       u8         must_have_num_of_obj1[0x1];
+       u8         support_num_of_obj1[0x1];
+       u8         must_have_index2[0x1];
+       u8         support_index2[0x1];
+       u8         must_have_index1[0x1];
+       u8         support_index1[0x1];
+       u8         segment_type[0x10];
+
+       u8         segment_name[4][0x20];
+
+       u8         index1_name[4][0x20];
+
+       u8         index2_name[4][0x20];
+};
+
+struct mlx5_ifc_resource_dump_segment_header_bits {
+       u8         length_dw[0x10];
+       u8         segment_type[0x10];
+};
+
+struct mlx5_ifc_resource_dump_command_segment_bits {
+       struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+
+       u8         segment_called[0x10];
+       u8         vhca_id[0x10];
+
+       u8         index1[0x20];
+
+       u8         index2[0x20];
+
+       u8         num_of_obj1[0x10];
+       u8         num_of_obj2[0x10];
+};
+
+struct mlx5_ifc_resource_dump_error_segment_bits {
+       struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+
+       u8         reserved_at_20[0x10];
+       u8         syndrome_id[0x10];
+
+       u8         reserved_at_40[0x40];
+
+       u8         error[8][0x20];
+};
+
+struct mlx5_ifc_resource_dump_info_segment_bits {
+       struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+
+       u8         reserved_at_20[0x18];
+       u8         dump_version[0x8];
+
+       u8         hw_version[0x20];
+
+       u8         fw_version[0x20];
+};
+
+struct mlx5_ifc_resource_dump_menu_segment_bits {
+       struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+
+       u8         reserved_at_20[0x10];
+       u8         num_of_records[0x10];
+
+       struct mlx5_ifc_resource_dump_menu_record_bits record[0];
+};
+
+struct mlx5_ifc_resource_dump_resource_segment_bits {
+       struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+
+       u8         reserved_at_20[0x20];
+
+       u8         index1[0x20];
+
+       u8         index2[0x20];
+
+       u8         payload[0][0x20];
+};
+
+struct mlx5_ifc_resource_dump_terminate_segment_bits {
+       struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+};
+
+struct mlx5_ifc_menu_resource_dump_response_bits {
+       struct mlx5_ifc_resource_dump_info_segment_bits info;
+       struct mlx5_ifc_resource_dump_command_segment_bits cmd;
+       struct mlx5_ifc_resource_dump_menu_segment_bits menu;
+       struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
+};
+
 enum {
        MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
        MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
@@ -2751,6 +2893,7 @@ union mlx5_ifc_hca_cap_union_bits {
        struct mlx5_ifc_fpga_cap_bits fpga_cap;
        struct mlx5_ifc_tls_cap_bits tls_cap;
        struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
+       struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;
        u8         reserved_at_0[0x8000];
 };
 
@@ -8817,6 +8960,28 @@ struct mlx5_ifc_mcam_access_reg_bits {
        u8         regs_31_to_0[0x20];
 };
 
+struct mlx5_ifc_mcam_access_reg_bits1 {
+       u8         regs_127_to_96[0x20];
+
+       u8         regs_95_to_64[0x20];
+
+       u8         regs_63_to_32[0x20];
+
+       u8         regs_31_to_0[0x20];
+};
+
+struct mlx5_ifc_mcam_access_reg_bits2 {
+       u8         regs_127_to_99[0x1d];
+       u8         mirc[0x1];
+       u8         regs_97_to_96[0x2];
+
+       u8         regs_95_to_64[0x20];
+
+       u8         regs_63_to_32[0x20];
+
+       u8         regs_31_to_0[0x20];
+};
+
 struct mlx5_ifc_mcam_reg_bits {
        u8         reserved_at_0[0x8];
        u8         feature_group[0x8];
@@ -8827,6 +8992,8 @@ struct mlx5_ifc_mcam_reg_bits {
 
        union {
                struct mlx5_ifc_mcam_access_reg_bits access_regs;
+               struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
+               struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
                u8         reserved_at_0[0x80];
        } mng_access_reg_cap_mask;
 
@@ -9432,6 +9599,13 @@ struct mlx5_ifc_mcda_reg_bits {
        u8         data[0][0x20];
 };
 
+struct mlx5_ifc_mirc_reg_bits {
+       u8         reserved_at_0[0x18];
+       u8         status_code[0x8];
+
+       u8         reserved_at_20[0x20];
+};
+
 union mlx5_ifc_ports_control_registers_document_bits {
        struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
        struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
@@ -9487,6 +9661,7 @@ union mlx5_ifc_ports_control_registers_document_bits {
        struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
        struct mlx5_ifc_mcc_reg_bits mcc_reg;
        struct mlx5_ifc_mcda_reg_bits mcda_reg;
+       struct mlx5_ifc_mirc_reg_bits mirc_reg;
        u8         reserved_at_0[0x60e0];
 };