spi: pxa2xx: Default thresholds to PXA configuration

[mirror_ubuntu-bionic-kernel.git] / include / linux / pxa2xx_ssp.h

diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h
index 2a097d176ba964faae345a245f516c447701553c..2d6f0c39ed6833b96f8aad03d9ed8b2e4d445add 100644 (file)
--- a/include/linux/pxa2xx_ssp.h
+++ b/include/linux/pxa2xx_ssp.h
@@ -83,7 +83,6 @@
 #define SSSR_RFS       (1 << 6)        /* Receive FIFO Service Request */
 #define SSSR_ROR       (1 << 7)        /* Receive FIFO Overrun */
 
-#ifdef CONFIG_ARCH_PXA
 #define RX_THRESH_DFLT 8
 #define TX_THRESH_DFLT 8
 
@@ -95,19 +94,16 @@
 #define SSCR1_RFT      (0x00003c00)    /* Receive FIFO Threshold (mask) */
 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
 
-#else
-
-#define RX_THRESH_DFLT 2
-#define TX_THRESH_DFLT 2
+#define RX_THRESH_CE4100_DFLT  2
+#define TX_THRESH_CE4100_DFLT  2
 
-#define SSSR_TFL_MASK  (0x3 << 8)      /* Transmit FIFO Level mask */
-#define SSSR_RFL_MASK  (0x3 << 12)     /* Receive FIFO Level mask */
+#define CE4100_SSSR_TFL_MASK   (0x3 << 8)      /* Transmit FIFO Level mask */
+#define CE4100_SSSR_RFL_MASK   (0x3 << 12)     /* Receive FIFO Level mask */
 
-#define SSCR1_TFT      (0x000000c0)    /* Transmit FIFO Threshold (mask) */
-#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
-#define SSCR1_RFT      (0x00000c00)    /* Receive FIFO Threshold (mask) */
-#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
-#endif
+#define CE4100_SSCR1_TFT       (0x000000c0)    /* Transmit FIFO Threshold (mask) */
+#define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6)       /* level [1..4] */
+#define CE4100_SSCR1_RFT       (0x00000c00)    /* Receive FIFO Threshold (mask) */
+#define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10)      /* level [1..4] */
 
 /* QUARK_X1000 SSCR0 bit definition */
 #define QUARK_X1000_SSCR0_DSS  (0x1F)          /* Data Size Select (mask) */